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Adventurer
Adventurer
3,369 Views
Registered: ‎09-30-2014

DQS to CK maximum on Zynq PS DDR Controller

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In some original documentation, there was a requirement that the DQS to CK relationship be no more that +/- 100 ps.  In the current UG933 there is no mention of such a requirements (only that CK be delayed longer than the longest DQS pair).  Is there still such a requirement?

 

Currently my design with have a delay of approximately 150 ps from the quickest DQS pair to the CK.  I want to make sure this is acceptable.  Otherwise I will have to somehow add an additional 300 mils to that group to achieve the +/- 100 ps requirement.

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Xilinx Employee
Xilinx Employee
4,506 Views
Registered: ‎07-30-2007

Re: DQS to CK maximum on Zynq PS DDR Controller

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The timing offsets are actually variable, driven by fine-adjustable DLLs. Thus the DS187 numbers can be seen as the timing given for a particular device's calibration results and board/DRAM specifics. In other words, the DS187 numbers are basically infinitely phase-shiftable from a board routing perspective- do not match your traces to it.
The point of keeping DQS<CK is that in order to shift the timing for DQS>CK, a clock inversion is used and more taps are used, which adds additional jitter, reducing margin. I've also had one customer report issues with this scheme, and since MIG also requires this, the requirement is now to keep DQS< CK length.

I hope this helps!
Dylan
4 Replies
Xilinx Employee
Xilinx Employee
3,345 Views
Registered: ‎07-11-2011

Re: DQS to CK maximum on Zynq PS DDR Controller

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HI,

 

Following other trace length figures of UG933 and CK trace equal or longer than the DQS trace per byte lane should not cause any issue

 

Regards,

Vanitha

 

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Adventurer
Adventurer
3,334 Views
Registered: ‎09-30-2014

Re: DQS to CK maximum on Zynq PS DDR Controller

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So, I agree if you only read UG933 that I would think that as long as the DQS length < CK then everything is ok.  But consider Tables 24 and 25 in DS187.   According to those, for 1066 Mb/s DDR3 Switching characteristics, Output Clock to DQS skew is spec'd as -0.11 to 0.09 of tCK.  For 1066 Mb/s, the tCK would be 1.87 ns.  So, if my calcultions are correct that would be a skew of -205 ps to 168 ps.  That implies that there is limit.  I can easily violate this limit and still meet the UG933 trace length requirements.  

 

Am I reading things correctly?  

 

Also, I assume the tCK in the DS187 is the speed at which you are actually running the DDR3 and not what the device is rated for?  I am planning on using a 1600 (1.25 ns tCK) rated DDR3, but running it at 1066 (1.87 ns tCK).  It seems to make sense you would have the skew based on the operating tCK, not the theoretical upper tCK bound.  Is this correct?

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Xilinx Employee
Xilinx Employee
4,507 Views
Registered: ‎07-30-2007

Re: DQS to CK maximum on Zynq PS DDR Controller

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The timing offsets are actually variable, driven by fine-adjustable DLLs. Thus the DS187 numbers can be seen as the timing given for a particular device's calibration results and board/DRAM specifics. In other words, the DS187 numbers are basically infinitely phase-shiftable from a board routing perspective- do not match your traces to it.
The point of keeping DQS<CK is that in order to shift the timing for DQS>CK, a clock inversion is used and more taps are used, which adds additional jitter, reducing margin. I've also had one customer report issues with this scheme, and since MIG also requires this, the requirement is now to keep DQS< CK length.

I hope this helps!
Dylan
Adventurer
Adventurer
3,278 Views
Registered: ‎09-30-2014

Re: DQS to CK maximum on Zynq PS DDR Controller

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Thanks for the clarification. This helps resolve our question about the relationship and consequently the length matching requirements and skew.
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