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Contributor
Contributor
944 Views
Registered: ‎04-19-2016

Disable Zynq ODT

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I'd like to use a single DDR3L chip with a Zynq (7-series) using series termination to save power, as suggested by Micron in TN-41-13. Therefore I need to disable the on die termination, and I believe I can disable it on the DDR side using DRAM_EMR_MR_reg as described in AR# 51744, but how do I do it on the Zynq side? It looks like I need to set reg_phy_*_local_odt and reg_ddrc_rank0_*_odt in DRAM_ODT_reg. However I can't see what the values set in reg_phy_*_local_odt actually mean, it just says "Value to drive on the 2-bit local_odt PHY outputs" in the TRM without saying what the local_odt values mean. It looks like the ps7_init file sets reg_phy_idle_local_odt to 3, so I assume that's disable? So to disable ODT entirely I should use DRAM_ODT_reg = 0x0003F240?

Anything else I'm missing before trying this?

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1 Solution

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Visitor johnzakelj
Visitor
116 Views
Registered: ‎08-26-2016

Re: Disable Zynq ODT

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Answer from Xilinx rep:
reg_phy_rd_local_odt[13:12] : Each bit is for the Rank (13th bit – Rank 1 & 12th Bit – Rank 0) and the value is to enable or disable the termination/buffer (1 = enable, 0 = disable)
reg_phy_wr_local_odt[15:14] : Each bit is for the Rank (15th bit – Rank 1 & 14th Bit – Rank 0) and the value is to enable or disable the termination/buffer (1 = enable, 0 = disable)
reg_phy_idle_local_odt[17:16] : Each bit is for the Rank (17th bit – Rank 1 & 16th Bit – Rank 0) and the value is to enable or disable the termination/buffer (1 = enable, 0 = disable)

12 Replies
Scholar watari
Scholar
922 Views
Registered: ‎06-16-2013

Re: Disable Zynq ODT

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Hi @patstew

 

"ODT function" has two items.

One is control signal to turn on/off ODT. (a)

The other is ODT value. (b)

 

I guess, you confuse a meaning of "ODT function"

 

In your case, I recommend to follow either followings.

 

(1) Set ODT value as disable by MRS/EMRS <- I strongly suggest it.

(2) Fix ODT signal as low <- You can not control ODT signal. But this value is always low.

 

Best regards,

 

 

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Contributor
Contributor
912 Views
Registered: ‎04-19-2016

Re: Disable Zynq ODT

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As I understand it both of those control the ODT in the DDR chip, but there is also ODT in the Zynq chip. Is that wrong?

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Scholar watari
Scholar
897 Views
Registered: ‎06-16-2013

Re: Disable Zynq ODT

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Hi @patstew

 

Here is a way to disable Zynq ODT.

You can choose best way for you.

But I recommend to use solution 1).

 

1) MRS (ODT value)

According to AR #51744, Zynq PS7 can issue MRS command when you modify ps7_init.tcl or ps7_init.c files.

It is 

 

2) ODT port

Zynq (PS) has ODT port for dram access. If you fix this signal as low by modified RTL or modified PCB, you can disable ODT function.

 

Best regards,

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Contributor
Contributor
891 Views
Registered: ‎04-19-2016

Re: Disable Zynq ODT

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There are two sets of termination resistors, one in the DDR and one in the Zynq. Normally the DDR terminates writes and the Zynq terminates reads. I'm fairly sure that both of your suggestions will only disable ODT at the DDR end of the link. I mentioned that AR#, and that I was planning to disable ODT at the DDR using MRS, in my original post.

I think the Zynq ODT is controlled by DRAM_ODT_reg, but it isn't fully documented as far as I can tell. What I really want to know is if local_odt = 3 means disable?

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Scholar watari
Scholar
865 Views
Registered: ‎06-16-2013

Re: Disable Zynq ODT

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Hi @patstew

 

Sorry. Maybe I'm misunderstanding.

 

Here is solution for you

1) Turn off ODT for write access

I already mentioned.

Would you refer it ?

 

2) Turn off ODT for read access

Yes. You can control ODT value and function.

You can change reg_phy_rd_local_odt (it is similer ODT value on DRAM).

Would you refer the following UG585 page 868 and 869 ?

 

https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

 

BTW, if you want to reduce power consumption, you can turn off DCI function, too.

If the result of signal integlity without DCI is fine, I recommend to turn off DCI function.

 

Best regards,

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Contributor
Contributor
851 Views
Registered: ‎04-19-2016

Re: Disable Zynq ODT

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Yep, I'm looking at page 868 and 869 of the TRM, and it says "Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress ... Typically this is set to the value required to enable termination at the desired strength for read usage." for reg_phy_rd_local_odt, but it doesn't say what writing 0, 1, 2 or 3 to that field actually does. Presumably they correspond to disable and 3 different termination strengths?

 

Thanks for the tip about DCI, I'll look at that.

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Scholar watari
Scholar
817 Views
Registered: ‎06-16-2013

Re: Disable Zynq ODT

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Hi @patstew

 

I'm not sure. But I think the followings.

 

2'b00 : ODT disable

2'b01 : 75ohm

2'b10 : 150ohm

2'b11 : 50ohm

 

Best regards,

 

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Visitor johnzakelj
Visitor
294 Views
Registered: ‎08-26-2016

Re: Disable Zynq ODT

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patstew,

Where you able to find a good definition for these register values?

The Zynq documentation UG933 explains the choice of VRN/VRP for proper calibration given a known trace impedance, but I have yet to find anything to set source/termination impedance to specific values using those reference resistors.  I am looking to enable ODT on the Zynq.

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Contributor
Contributor
275 Views
Registered: ‎04-19-2016

Re: Disable Zynq ODT

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No sorry, the only answer I've got is that one above from watari, but that doesn't tie up with Xilinx setting 3 for idle, which I'd expect to be disable. At some point I need to measure it.

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Visitor johnzakelj
Visitor
243 Views
Registered: ‎08-26-2016

Re: Disable Zynq ODT

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I agree that watari's response does not add up.

I find that setting DRAM_ODT_reg to anything other than 0x00000248 (default is 0x0003c248) causes my custom board with DDR3 to crash.  I realize this is likely a hardware issue, but I need to have a definition of these bits to understand how this setting affects the hardware.

If anyone can fill in these question marks, please let me know.  Thanks!

reg_phy_rd_local_odt: 0b00 = ?, 0b01 = ?, 0b10 = ?, 0b11 = ?

reg_phy_wr_local_odt: 0b00 = ?, 0b01 = ?, 0b10 = ?, 0b11 = ?

reg_phy_idle_local_odt: 0b00 = ?, 0b01 = ?, 0b10 = ?, 0b11 = ?

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Visitor johnzakelj
Visitor
117 Views
Registered: ‎08-26-2016

Re: Disable Zynq ODT

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Answer from Xilinx rep:
reg_phy_rd_local_odt[13:12] : Each bit is for the Rank (13th bit – Rank 1 & 12th Bit – Rank 0) and the value is to enable or disable the termination/buffer (1 = enable, 0 = disable)
reg_phy_wr_local_odt[15:14] : Each bit is for the Rank (15th bit – Rank 1 & 14th Bit – Rank 0) and the value is to enable or disable the termination/buffer (1 = enable, 0 = disable)
reg_phy_idle_local_odt[17:16] : Each bit is for the Rank (17th bit – Rank 1 & 16th Bit – Rank 0) and the value is to enable or disable the termination/buffer (1 = enable, 0 = disable)

Contributor
Contributor
32 Views
Registered: ‎04-19-2016

Re: Disable Zynq ODT

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It seems setting the local_odt bits doesn't make a great deal of difference. Setting DCI_TYPE = 0 and TERM_EN = 0 in DDRIOB_xxx does save a significant amount of power though.

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