01-27-2015 05:12 AM
Anyone know where to find information about the cores found in the proc_common library (apart from browsing the code)? My googling has come up empty.
I am trying to get to grips with a custom IP that makes extensive use of stuff like async_fifo_fg, srl_fifo_f etc. and even though each of the IPs are pretty simple, when I want to replace e.g. a synchronous FIFO with an asynchronous d.o. it would be great if there was some place to look for guidance. I hate to have to resort to IT archeology (AKA reverse engineering) when there should be documentation around...
03-13-2015 02:39 AM - edited 03-13-2015 04:04 AM
Not much activity from this post, maybe I should interpret this as "Do not use the proc_common core library by yourself!". I just shot myself in the foot by attempting to generate a synchronous FIFO with different data size on write and read ports by inserting a sync_fifo_fg with the following generic settings:
.C_ENABLE_RLOCS (0), // not supported in sync fifo
.C_MEMORY_TYPE (1), // 0 = distributed RAM, 1 = BRAM
.C_PRELOAD_REGS (1), // 1 = first word fall through
.C_PRELOAD_LATENCY (0), // 0 = first word fall through
It looked OK, but throws a fatal in simulation:
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 32 (31 downto 0). Right is 8 (7 downto 0). # Time: 4545 ns Iteration: 11 Process: /system_tb/dut/yuv444_nv12_recoder_0/yuv444_nv12_recoder_0/USER_LOGIC_I/recoder/y_fifo_inst/V6_S6_AND_LATER/I_SYNC_FIFO_BRAM/gconvfifo/inst_conv_fifo/gen_ss/fgss/gnll_dout/gbm_dout/rd_mem File: C:/dev/Xilinx/14.7/ISE_DS/ISE/vhdl/src/XilinxCoreLib/fifo_generator_v9_3.vhd
Turns out there is a local variable that in this case gets the size (7 DOWNTO 0) that is assigned to a signal of size (31 DOWNTO 0). Trying to see what CoreGen would have done in the same situation, I realized that different data widths are not supported in synchronous FIFOs, so the real culprit here is me abusing fifo_generator.
This would probably not have happened if there was some documentation, so I just bring it up to bump the thread. As for me, I guess it is back to CoreGen...
P.S. And yes, I checked the asynchronous counterpart in proc_common, async_fifo_fg. Funny enough, that one has only one generic for data-width, making it impossible to configure different read and write port widths even though it is possible to configure an asynchronous FIFO in CoreGen, using the exact same fifo_generator, with this feature. D.S.
03-13-2015 07:39 AM
once i tried what you would do.. then i simply used the CoreGen functions (like fifos) and instantiated them in my custom ip