UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
2,226 Views
Registered: ‎04-18-2015

Dynamic clock reconfiguration for zynq

Jump to solution

Hi,

 

I refer the Clocking Wizard v5.3 page 54-55 to reconfiguration my clock on the fly.

https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_3/pg065-clk-wiz.pdf

 

However, whenever I try to read from or write to the dynamic reconfiguration registers, my code halt there forever until I terminate the running.

 

For example, I want to reconfigure my 50MHz clock to 50MHz, I use the code below:

Xil_Out32(XPAR_CLK_WIZ_0_BASEADDR+ 0x200, 0x00000101);

Xil_Out32(XPAR_CLK_WIZ_0_BASEADDR+ 0x208, 0x00000001); 
Xil_Out32(XPAR_CLK_WIZ_0_BASEADDR+ 0x25C, 0x00000003);

But the code stop at the first line and never move again.

 

Could you anyone give me a direction to look into this issue?

 

Best wishes,

Lei

 

0 Kudos
1 Solution

Accepted Solutions
Teacher muzaffer
Teacher
3,740 Views
Registered: ‎03-31-2012

Re: Dynamic clock reconfiguration for zynq

Jump to solution

@d4223738 I think it would be a good idea to divide the interconnect into two and completely separate the two clock domains. It would be much easier to prove that there is no hidden dependency. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
7 Replies
Teacher muzaffer
Teacher
2,213 Views
Registered: ‎03-31-2012

Re: Dynamic clock reconfiguration for zynq

Jump to solution

@d4223738 are you by any chance using the output of this pll/mmcm to talk to PL ? If so, you are basically shooting yourself in the foot and asking why it hurts ;-).  Make sure that you're not disabling a clock path which the PL needs to talk to PS.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Adventurer
Adventurer
2,181 Views
Registered: ‎04-18-2015

Re: Dynamic clock reconfiguration for zynq

Jump to solution

Hi @muzaffer,

 

Thank you for the reply.

 

I just checked my design which is a SoC with Zynq and MicroBlaze, they simply share a BRAM through the same BRAM controller to transfer data.

 

I use 2 clocks from the PS:

-Clock0 is used to clock the Zynq M_AXI_GP0_ACLK, AXI interconnect, slave port on the AXI interconnect (for Zynq), the AXI clock of BRAM and clock wiz

 

-clock1 is used as the clk_in of clock wiz only

 

The clk_out of the clock wiz is used to dynamically configure the MicroBlaze and its local memory and debug module, and slave ports on the AXI interconnect (for MicroBlaze)

 

I think the clock 0 in this case is the path which PL needs to talk to PS, am I correct? Do I miss any module in my design or any steps in my code?

 

Best wishes,

Lei

0 Kudos
Teacher muzaffer
Teacher
2,144 Views
Registered: ‎03-31-2012

Re: Dynamic clock reconfiguration for zynq

Jump to solution

@d4223738 can you post your block diagram?

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Adventurer
Adventurer
2,142 Views
Registered: ‎04-18-2015

Re: Dynamic clock reconfiguration for zynq

Jump to solution

Hi @muzaffer,

 

Thank you.

 

The block diagram is shown below:

1. FLCK_CLK0

FLCK_CLK0.png

 

2. FCLK_CLK1

FLCK_CLK1.png

 

3. clk_out

clk_out.png

0 Kudos
Teacher muzaffer
Teacher
3,741 Views
Registered: ‎03-31-2012

Re: Dynamic clock reconfiguration for zynq

Jump to solution

@d4223738 I think it would be a good idea to divide the interconnect into two and completely separate the two clock domains. It would be much easier to prove that there is no hidden dependency. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Adventurer
Adventurer
2,073 Views
Registered: ‎04-18-2015

Re: Dynamic clock reconfiguration for zynq

Jump to solution

Hi @muzaffer,

 

Thanks for the help. Your method works. Now, these codes can be executed without any issues.

 

However, I am wondering if there is any way that I can use to check the value of new frequency? Because I am not sure whether the clock reconfiguration is successful.

 

The MicroBlaze in my design is running an infinite loop with some code inside. After the clock reconfiguration, it stops.

 

Is this clock reconfiguration able to change the clock of MicroBlaze on the fly?

 

Best wishes,

Lei

0 Kudos
Teacher muzaffer
Teacher
2,061 Views
Registered: ‎03-31-2012

Re: Dynamic clock reconfiguration for zynq

Jump to solution

@d4223738 if your current issue is solved, it makes sense to close this thread and open a new one with the new issue. Dynamically changing the frequency of a processor takes some tender love & care :-)

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos