UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
478 Views
Registered: ‎09-19-2017

Error while launching program: bitstream is not compatible with the target revision bitstream is not compatible with the target revision

Jump to solution

Holle,

   tool: SDSoC2017.1->Vivado->SDK

   board:  Avnet UltraZed-3EG IO Carrier Card

   Problem is: when I generate a bitstream and I try to program FPGA in SDK, I get "bitstream is not compatible with the target revision bitstream is not compatible with the target revision".As fig.1, fig2.

fig.12.png

          I found that there is not "Parts" named "xczu3eg-sfva625-1-i-es1", when I created simple design according to this tutorial"http://zedboard.org/content/ulrazed-board-preset-files-vivado-20172" and "http://zedboard.org/content/ultrazed-board-file-20164-not-getting-detected-vivado". AS fig.3.

3.png

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Contributor
Contributor
664 Views
Registered: ‎09-19-2017

Re: Error while launching program: bitstream is not compatible with the target revision bitstream is not compatible with the target revision

Jump to solution
0 Kudos
1 Reply
Highlighted
Contributor
Contributor
665 Views
Registered: ‎09-19-2017

Re: Error while launching program: bitstream is not compatible with the target revision bitstream is not compatible with the target revision

Jump to solution
0 Kudos