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Visitor clarkgable
Visitor
502 Views
Registered: ‎08-23-2018

Establish SGMII Fixed Link connection to Zynq UltraScale + MPSoCs

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Hi .*,

 

I’m currently working on a project using the Xilinx Zynq UltraScale + MPSoCs processor (more detailed, the XCZU3EG processor). I am trying to establish a PHY-less SGMII connection (MAC - MAC) to a broadcom switch on GEM2 / eth0. I already have a working RGMII to PHY connection on GEM3 / eth1.

The configuration for the GEM2 port in the vivado project is enabled to GT Lane2 and its MDIO port is disabled. The clock source for GEM2 is "Ref Clk3" and is set to 125 MHz.

 

If I check the ifconfig output, the link for eth0 is up:

 

ifconfig.png

 

However, the link_status (bit 2) in pcs_status (GEM) is always at 0. Do you have any help or idea?

My device tree looks like that:

 

eth0: ethernet@ff0d0000 {
		compatible = "cdns,zynqmp-gem";
		status = "okay";
		interrupt-parent = <0x4>;
		interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>;
		reg = <0x0 0xff0d0000 0x0 0x1000>;
		clock-names = "pclk", "tx_clk", "hclk";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		#stream-id-cells = <0x1>;
		iommus = <0xe 0x876>;
		power-domains = <0x15>;
		clocks = <0x3 0x2f 0x3 0x2f 0x3 0x33>;
		xlnx,ptp-enet-clock = <0x0>;
		phy-mode = "sgmii";
		fixed-link = <0 1 1000 0 0>; 
}

I replaced the phy-mode "moca" with "sgmii", since the GEM2 was in reset state with moca.

My details for the sgmii connection are:

  • speed: 1000
  • Full duplex
  • No auto-negotiation

I tried to loopback it, as mentioned in AR# 69483, and after that the link was up.

Thanks in advance, any help or discussion is appreacheated!

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Visitor clarkgable
Visitor
434 Views
Registered: ‎08-23-2018

Re: Establish SGMII Fixed Link connection to Zynq UltraScale + MPSoCs

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Hi @stephenm,

 

thanks for your help. I solved my issue now.

However, in my case the Zynq did not enable the SGMII connection initially (problably through the "phy-mode=moca" setting in the device-tree). Therefore, I had to enable it manually in the register:

  1. Register 0xFF0D0004 with value 0x8328c5a to enable SGMII
  2. Register 0xFF0D0200 with value 0x140 to disable Auto-Negotiation
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Moderator
Moderator
480 Views
Registered: ‎09-12-2007

Re: Establish SGMII Fixed Link connection to Zynq UltraScale + MPSoCs

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Visitor clarkgable
Visitor
435 Views
Registered: ‎08-23-2018

Re: Establish SGMII Fixed Link connection to Zynq UltraScale + MPSoCs

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Hi @stephenm,

 

thanks for your help. I solved my issue now.

However, in my case the Zynq did not enable the SGMII connection initially (problably through the "phy-mode=moca" setting in the device-tree). Therefore, I had to enable it manually in the register:

  1. Register 0xFF0D0004 with value 0x8328c5a to enable SGMII
  2. Register 0xFF0D0200 with value 0x140 to disable Auto-Negotiation
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