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Visitor ygk13
Visitor
8,746 Views
Registered: ‎10-18-2015

Ethernet via EMIO error "Set clk to 0Hz"

Hi,

 

I'm trying to make Ethernet via EMIO work on my Zynq-7000 custom board.

 

As described in the file attached, external PHY(DP83848C, TI) is connected to PS GEM0 via MII2RMII IP in my design.

Ethernet clock source is "external" and the frequency is set to 2.5MHz in vivado block design.

 

After successfully booting linux kernel, Link-up LED is on, but ping doesn't work.

Also, I got the message below on UART.

> xemacps e000b000.ethernet: Set clk to 0Hz

> xemacps e000b000.ethernet: link up (10/HALF)

 

My guess is that something is wrong with ethernet clk. It should be set to 2.5MHz, not 0Hz.

How can I set the clock frequency as intended?

 

Any advice on this design would be appreciated.

 

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7 Replies
Visitor ygk13
Visitor
8,727 Views
Registered: ‎10-18-2015

Re: Ethernet via EMIO error "Set clk to 0Hz"

some posts implies that the message "set clk to 0Hz" can be involved in device tree files.

https://forums.xilinx.com/t5/Embedded-Linux/zynq-linux-dual-emacps-gem-problem/td-p/263964/page/4

 

The following is "system-top.dts" in my petalinux.

>&gem0 {
>phy-handle = <&phy0>;
>mdio {
>#address-cells = <1>;
>#size-cells = <0>;
>phy0: phy@0 {
>compatible = “national semiconductor, DP83848C”;
>device_type = “ethernet-phy”;
>reg = <0>;
>};
>};
>};

 

Is there anything wrong?

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Xilinx Employee
Xilinx Employee
8,693 Views
Registered: ‎08-01-2008

Re: Ethernet via EMIO error "Set clk to 0Hz"

To resolve this issue, Change the value of CONF_TMEOUT_MAX from (HZ*30) to (HZ*1)

#define CONF_TIMEOUT_MAX (HZ*1)

This can be found in the ipconfig.c file here:

/opt/pkg/petalinux-v2013.10-final/components/linux-kernel/xlnx-3.8/net/ipv4/ipconfig.c
Thanks and Regards
Balkrishan
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Visitor ygk13
Visitor
8,567 Views
Registered: ‎10-18-2015

Re: Ethernet via EMIO error "Set clk to 0Hz"

I've edited ipconfig.c file and checked the connection, but still it doesn't work.

 

Changing the value of CONF_TMEOUT_MAX is introduced in AR#60820.

The AR seems not to be in my case because its clock frequency is set correctly.

>xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz

>xemacps e000b000.ps7-ethernet: link up (1000/FULL)

 

AR#60820

http://japan.xilinx.com/support/answers/60820.html

 

Thanks for your reply!

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Visitor ygk13
Visitor
8,228 Views
Registered: ‎10-18-2015

Re: Ethernet via EMIO error "Set clk to 0Hz"

> xemacps e000b000.ethernet: Set clk to 0Hz

> xemacps e000b000.ethernet: link up (10/HALF)

 

Does this frequency (0Hz) reflect the real frequency of the clock that Zynq receives, 

or frequency set in vivado block design?

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Xilinx Employee
Xilinx Employee
8,224 Views
Registered: ‎08-01-2008

Re: Ethernet via EMIO error "Set clk to 0Hz"

check related post
https://forums.xilinx.com/t5/Embedded-Linux/xemacps-e000b000-ps7-ethernet-eth0-no-PHY-setup/td-p/499018
Thanks and Regards
Balkrishan
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Visitor ygk13
Visitor
7,981 Views
Registered: ‎10-18-2015

Re: Ethernet via EMIO error "Set clk to 0Hz"

Thanks for your reply :)

 

Referring to the post, I've checked PHY address, but it seems to be set collectly.

PHY address set on my board corresponds with one written in device tree files.

 

 

Ethernet PHY on my board is DP83848C made by TI, and compatible type of PHY is designated in system-top.dts as follows.

>compatible = “national semiconductor, DP83848C”;

Is this OK?

 

Any suggestion will be appreciated.

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Visitor whennig
Visitor
3,212 Views
Registered: ‎04-10-2017

Re: Ethernet via EMIO error "Set clk to 0Hz"

Here are a few key steps I had to do to connect the Zynq GEM0 via EMIO to a DP83640 demo board.

Using a MicroZed 7010 with a custom carrier board to bring out PL pins and wire them to the DP83640 demo board.

The MicroZed runs Linaro/Ubuntu 15 with a kernel compiled from a recent (~3/10/17) download from

https://github.com/Xilinx/linux-xlnx

 

1) block diagram connections as in original post.

- configure MIItoRMII IP for “Zynq PS Gigabit Ethernet Controller", check both boxes for speed

- use DP83640's 50 MHz clk as ref_clk

- connect rst_n to "1"
  (initially I tied it to 0 as the wrapper just called it "reset_rtl" with no indication of active low, wich of course didn't work)

 

2) Kernel configuration: turn on the following

- CONFIG_NET_VENDOR_NATSEMI=y

- CONFIG_NATIONAL_PHY=y

- CONFIG_DP83640_PHY=y       (for my particular PHY, listed under PTP support, not MII PHYs)

 

3) Device tree

       gem0: ethernet@e000b000 {
             #address-cells = <1>;
            #size-cells = <0>;
            clock-names = "ref_clk", "aper_clk";
            clocks = <&clkc 13>, <&clkc 30>;
            compatible = "xlnx,ps7-ethernet-1.00.a";
            interrupt-parent = <&intc>;
            interrupts = <0 22 4>;
            local-mac-address = [00 0a 35 19 00 00];    // just to be different
            phy-handle = <&phy0>;
            phy-mode = "gmii";                                                  // notice change from default
            reg = <0xe000b000 0x1000>;
            xlnx,eth-mode = <0x1>;
            xlnx,has-mdio = <0x1>;
            xlnx,ptp-enet-clock = <111111115>;
            mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                phy0: phy@1 {                                                    // notice change from default
                    compatible = "NatSemi,DP83640";                  // notice change from default
                    device_type = "ethernet-phy";
                    reg = <1>;                                                       // notice change from default
                } ;
          } ;
        } ;

the "phy reg" number <1> was found by trial and error

 

 

Result:

xemacps_DP83640.png

While it reports clk 0 Hz, I have a working connection through our local network

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