UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Scholar ronnywebers
Scholar
1,854 Views
Registered: ‎10-10-2014

GP Master AXI interface 'static remap' and 'thread ID width'

I'm looking for a more detailed explanation of the Zynq configuration options :

 

- static remap (Enables static remap for GP0 interface)

- thread ID width

 

what do both options mean? Is it documented somewhere?

 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos