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Adventurer
Adventurer
3,555 Views
Registered: ‎10-24-2016

GPIO removed in synthesis

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Hello, 

 

I am trying to create a Microblaze system through XPS and I am having problems to connect a custom IP to GPIO inputs in Microblaze system. I have two GPIO ports ( 32 bits and 2 bits. All inputs) and it doesnt mind how I create my custom core, always synthesis remove my core.

 

When I run synthesis i get the following warnings:

 

fallo.png

 

Does this mean that GPIOs of Microblaze system always have to be connected to external ports??

 

thanks for your answers. 

 

Regards

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Adventurer
Adventurer
6,132 Views
Registered: ‎10-24-2016

Re: GPIO removed in synthesis

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If anyone has the same problem, it has been solved deleting IO ports on MHS file. 

 

I don't know why removing ports from XPS GUI, or cleaning project files is not enough. Ports must be removed manually from the MHS file. 

 

Hope this helps to someone with the same problem.

 

 

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6 Replies
Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: GPIO removed in synthesis

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@alxtrnk it's possible that something in your IP core is causing this removal. Show the connectivity of the IP core and its connection to MB. Also make sure you simulate the IP core for correct functionality.

Finally if you are connecting only input GPIOs where does the IP get its input? Is there any chance that the IP receives no inputs so its behavior is entirely predictable which causes it to be removed?

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Adventurer
Adventurer
3,472 Views
Registered: ‎10-24-2016

Re: GPIO removed in synthesis

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Hi @muzaffer. Thanks a lot for your answer, and sorry for my late answer. I have not been in the office until today.

 

I have implemented the solution proposed by johnmcd in this post:

 

https://forums.xilinx.com/t5/Embedded-Development-Tools/Microblaze-GPIO-interfaces-to-be-used-by-internal-logic-not-the/td-p/199511

 

Basically the solution is to connect GPIO input ports in XPS in this way:

 

gpio_conn.png

 

But still doesnt work, GPIOs inputs in microblaze always read "0".

 

This is the code of my peripheral. It is a simple core controlled by an external switch. If switch is active, first I put signal "ready" to logic '1' to tell the processor that data is ready to be read (GPIO port 2, 1 input). In the same way, I send 32 bits of data to Microblaze through GPIO port 1 (32 inputs). I have also added an external signal directly activated by external switch only to know that external switch is giving me a high level when pushed. This output ( mirror input of the switch is working ok), but GPIO read in microblaze always read "0" in port 1 and in port 2.

 

 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:31:09 02/20/2017 
-- Design Name: 
-- Module Name:    gpio_generator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gpio_generator is
    Port ( clk : in  STD_LOGIC;
			  reset : in std_logic;
			  start : in std_logic;  -- external input pushbutton
			  start_received : out std_logic ; -- external output to check if switch is working well.
           data : out  STD_LOGIC_VECTOR (31 downto 0); -- directly connected to processor GPIO port 1
           ready : out  STD_LOGIC); -- directly connected to processor GPIO port 2
end gpio_generator;

architecture Behavioral of gpio_generator is

signal data_reg : std_logic_vector (31 downto 0):= (others =>'0'); -- reg for data to be sent to the processor

begin

data <= data_reg;

process (clk, reset)

begin

if (reset = '0') then
	data_reg <= (others =>'0');
	ready <= '0';
elsif (clk'event and clk = '1') then

if ( start = '1') then  -- external switch activated

	data_reg <= std_logic_vector (unsigned (data_reg) + 1);  -- data reg = data_reg +1
	ready <= '1'; 
	start_received <= '1';
	if (data_reg = X"000000FF") then -- if data_reg reaches 0x000000FF, it starts from zero again.
		data_reg <= X"00000000";
	else
		null;
	end if;
else
	data_reg <= (others=>'0');
	ready <= '0';
	start_received <= '0';
	
end if;

end if;

end process;

end Behavioral;

And this is the code on microblaze. Also very simple:

 

 

 

/*
 *
 /*
 *
 * Xilinx, Inc.
 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
 * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
 * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE.
 */

/*
 * 
 *
 * This file is a generated sample test application.
 *
 * This application is intended to test and/or illustrate some 
 * functionality of your system.  The contents of this file may
 * vary depending on the IP in your system and may use existing
 * IP driver functions.  These drivers will be generated in your
 * SDK application project when you run the "Generate Libraries" menu item.
 *
 */


#include <stdio.h>
#include "xparameters.h"
#include "xil_cache.h"
#include "xintc.h"
#include "intc_header.h"
#include "xuartlite.h"
#include "uartlite_header.h"
#include "uartlite_intr_header.h"
#include "xbasic_types.h"
#include "xgpio.h"
#include "gpio_header.h"
#include "gpio_intr_header.h"


#define GPIO_CHANNEL1 1
#define GPIO_CHANNEL2 2

#define MEM_BASE_ADDRESS XPAR_MCB_DDR3_S0_AXI_BASEADDR


XGpio Gpio; /* The Instance of the GPIO Driver */


int main() 
{

   int Status;
   u32 *RxPointer;
   static XIntc intc;
   static XUartLite debug_module_UartLite;
   static XGpio axi_gpio_0_Gpio;

   Xil_ICacheEnable();
   Xil_DCacheEnable();

   print("---Entering main---\n\r");

   Status = XGpio_Initialize(&Gpio, XPAR_AXI_GPIO_0_DEVICE_ID);
   if (Status != XST_SUCCESS) {
	return XST_FAILURE;
   }
   
   XGpio_SetDataDirection(&Gpio, GPIO_CHANNEL1, 1);
   XGpio_SetDataDirection(&Gpio, GPIO_CHANNEL2, 1);

   RxPointer = (u32*) MEM_BASE_ADDRESS;

   while (1)
   {
	   if( (XGpio_DiscreteRead(&Gpio, GPIO_CHANNEL2)) != 0)
	   {
		   	  *RxPointer = XGpio_DiscreteRead (&Gpio, GPIO_CHANNEL1);
			   xil_printf ("%d/n/r",*RxPointer);
			   RxPointer = RxPointer + 4;
	   }
	   else
	   {
		  print ("data not ready \n\r");
	   }
   }

   Xil_ICacheDisable();
   Xil_DCacheDisable();

}

 

So I dont know where can be the problem. I suppose it is in the connections of GPIO module to internal logic, but i have followed the solution proposed in the link added before and the warning has dissapeared, but the inputs are not being read correctly. 

 

These are the connections in my top level module if it helps ( ISE Schematic):

 

gpio_connections.png

 

Hope you can drive me in the right direction to continue. 

 

thanks by advance. 

 

Regards.

 

 

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Adventurer
Adventurer
3,449 Views
Registered: ‎10-24-2016

Re: GPIO removed in synthesis

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Hi again @muzaffer

 

I dont know how i did it this morning, but i have tried to create another XPS project with microblaze and 2 GPIO modules, and now i am getting this error message. I have done the same as explained before ( solution proposed by @johnmcd):

 

edk_error.png

 

So now, i am completely lost about how to connect correctly GPIO ports to internal fabric.

 

Let me know if you think i am doing something wrong. 

 

Thanks again by advance. 

 

Regards.

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Adventurer
Adventurer
3,410 Views
Registered: ‎10-24-2016

Re: GPIO removed in synthesis

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Ok..........

 

I will open a webcase for this issue and one more not answered by the forum users. 

 

If i receive a solution i will post it for the rest of people with the same problem and with no support by anyone. 

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Adventurer
Adventurer
3,402 Views
Registered: ‎10-24-2016

Re: GPIO removed in synthesis

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Webcase is no longer available since few years ago....................

 

This is really frustrating........

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Highlighted
Adventurer
Adventurer
6,133 Views
Registered: ‎10-24-2016

Re: GPIO removed in synthesis

Jump to solution

If anyone has the same problem, it has been solved deleting IO ports on MHS file. 

 

I don't know why removing ports from XPS GUI, or cleaning project files is not enough. Ports must be removed manually from the MHS file. 

 

Hope this helps to someone with the same problem.

 

 

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