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6,035 Views
Registered: ‎02-23-2016

Generate a MCS file is not working as expected

Hello,

 

I have a project for the ZC702 board. In this project I am using only the logic of the FPGA and the two ARMs are not in use at all. The .bit file is generated properly and is working fine, after download it via the JTAG the configuration is correct.

 

Now I would like to program the configuration device to avoid the need to use the JTAG every time the board is powered up.

 

In the bitstream options I ask to generate a .bin file, but for documentation it seems that is missing the header. For this reason I use the following command:

 

write_cfgmem -format mcs -interface SPIx1 -size 128 -loadbit "up 0x0 system.bit" -file boot.mcs

 

I load the file on the memory, no errors or warnings but the Init led stays red.

 

Any ideas how to debug this?

 

 

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4 Replies
Scholar pratham
Scholar
6,017 Views
Registered: ‎06-05-2013

Re: Generate a MCS file is not working as expected

@abelardogonzalez You cannot use flash directly to program the PL of zynq when not using the processors. Flash on the board is for PS configuration. Please take a look at the bist.pdf about how design is created and how to program the onboard qspi flash using sdk. Pdf can be found here

https://secure.xilinx.com/webreg/clickthrough.do?cid=413504

-Pratham

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Moderator
Moderator
6,007 Views
Registered: ‎07-31-2012

Re: Generate a MCS file is not working as expected

Moved to appropriate board


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Moderator
Moderator
6,006 Views
Registered: ‎07-31-2012

Re: Generate a MCS file is not working as expected

Hi,

 

This will not work unless you have processor in your hardware design.

Try to add processor and  interface to SPI Flash.

Refer from page 13 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf 

 

Regards

Praveen


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Xilinx Employee
Xilinx Employee
6,001 Views
Registered: ‎07-23-2012

Re: Generate a MCS file is not working as expected

In Zynq, PS is master and PL is slave. Quad SPI flash is connected to Quad SPI controller on PS side. To configure PL, you should create a Zynq boot image using SDK that contains FSBL (to initialize PS and defines the partitions of boot image) and bit file.

Once PS is initialized, PL will be configured.

This document-http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug873-zynq-ctt.pdf has list of documents that will guide you through this flow.

I would also recommend you to study chapter 6 of UG585 to understand Zynq boot flow.
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