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Participant hacmachdien
Participant
5,041 Views
Registered: ‎04-04-2013

Global clock pin on the PL side

Hi everyone, I'm implementing a simple design on the PL side of Zynq but stuck with clock assigment. Where can I get a global clock pin and feed it to my design? I'm well aware that there are MRCC and SRCC pins that I can connect my clk signal to. However, when I monitor one of these MRCC, SRCC pins I get nothing but some erratic pulses, not proper clock signal. Have anybody been encounter this problem before? 

PS: I don't want to mess with the PS side of the chip and my clk is single-ended so I know that I have to wire it to positive ends of the differential MRCC, SRCC pins.

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5 Replies
Community Manager
Community Manager
5,030 Views
Registered: ‎06-14-2012

Re: Global clock pin on the PL side

When connecting a single-ended clock to the differential CC pair of pins, it must be connected to the
positive (P) side of the pair. The MRCC (multi-region) pins, when used as single-region resource, can drive four
BUFIOs and four BUFRs in a single bank. Please check the following pinout guide. Hope this helps.

 

http://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf

 

Regards

Sikta

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Participant hacmachdien
Participant
5,022 Views
Registered: ‎04-04-2013

Re: Global clock pin on the PL side

Thanks siktap,
As I mentioned above I'm aware of the fact that I have to wire my clk signal to the positive side of the differential clock pair. Actually, I am trying to extract the PL clock source and bring it to my design, not to connect an external clock to drive the PL. I wonder if the SYSTEM CLOCK (200 MHz) on the D18 pin can be wired to my design.
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Community Manager
Community Manager
5,013 Views
Registered: ‎06-14-2012

Re: Global clock pin on the PL side

Is it a PL AXI clock?

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Participant hacmachdien
Participant
5,003 Views
Registered: ‎04-04-2013

Re: Global clock pin on the PL side

This description of D18 pin is taken from "Xilinx UG850 ZC702 Evaluation Board User Guide":

The system clock source is an LVDS 200 MHz oscillator at U43. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 35. The signal pair is named SYSCLK_P and SYSCLK_N and each signal is connected to U1 pins D18 and C19 respectively on the XC7Z020 AP SoC.

 

Capture.JPG

I did try this clock source once, but I don't get anything  when I check it on ChipScope Pro. 

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Xilinx Employee
Xilinx Employee
4,995 Views
Registered: ‎08-01-2012

Re: Global clock pin on the PL side

Make sure that IO standard  & voltage of of both interfacing pins are same.

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