04-14-2014 08:03 PM
Hi everyone, I'm implementing a simple design on the PL side of Zynq but stuck with clock assigment. Where can I get a global clock pin and feed it to my design? I'm well aware that there are MRCC and SRCC pins that I can connect my clk signal to. However, when I monitor one of these MRCC, SRCC pins I get nothing but some erratic pulses, not proper clock signal. Have anybody been encounter this problem before?
PS: I don't want to mess with the PS side of the chip and my clk is single-ended so I know that I have to wire it to positive ends of the differential MRCC, SRCC pins.
04-14-2014 08:56 PM
When connecting a single-ended clock to the differential CC pair of pins, it must be connected to the
positive (P) side of the pair. The MRCC (multi-region) pins, when used as single-region resource, can drive four
BUFIOs and four BUFRs in a single bank. Please check the following pinout guide. Hope this helps.
04-14-2014 09:19 PM
04-14-2014 11:54 PM
This description of D18 pin is taken from "Xilinx UG850 ZC702 Evaluation Board User Guide":
The system clock source is an LVDS 200 MHz oscillator at U43. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 35. The signal pair is named SYSCLK_P and SYSCLK_N and each signal is connected to U1 pins D18 and C19 respectively on the XC7Z020 AP SoC.
I did try this clock source once, but I don't get anything when I check it on ChipScope Pro.
04-15-2014 02:16 AM
Make sure that IO standard & voltage of of both interfacing pins are same.