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Observer kane06
Observer
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Registered: ‎01-21-2019

How to align different data width in different memories?

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Hi, my project need to load data to a special ram with data width of something weird like 300 bit, for now I'm using a bram controller connected to CDMA. With this 300-bit width, it's clear that I cannot just connect my ram to controller directly.

Is there any solution for this issue? I'm thinking about creating a module to concatenate a group of input data to get a 300-bit output and calculate a new address.

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: How to align different data width in different memories?

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Hello @kane06 

It sounds like your initial idea of a custom IP would be best for this, as it sounds like a weird data-packing issue.  You might be able to get away with the AXI Data Width Converter inside of the AXI Interconnect or AXI SmartConnect, but I am not sure that will adequately handle changing to such a unique bit-width.

Thanks,
Caleb
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Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎01-09-2019

Re: How to align different data width in different memories?

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Hello @kane06 

It sounds like your initial idea of a custom IP would be best for this, as it sounds like a weird data-packing issue.  You might be able to get away with the AXI Data Width Converter inside of the AXI Interconnect or AXI SmartConnect, but I am not sure that will adequately handle changing to such a unique bit-width.

Thanks,
Caleb
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Observer kane06
Observer
205 Views
Registered: ‎01-21-2019

Re: How to align different data width in different memories?

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Thank you @calebd . As implemention of AXI sounds much harder, I'll keep it to a custom module and place it between BRAM controller and BRAM.

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