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Explorer
Explorer
2,827 Views
Registered: ‎12-06-2013

How to create a burst transaction by a Zynq AXI GP Master?

I created an AXI3-AXI4L protocol converter that assumes a well behaved Zynq single AXI3 transaction. Well, there are bursts that show up periodically which of course lock up the AXI bus because my converter doesn't support bursts. The problem is I don't know how the software guys create a burst (and they don't either) and we have been unable to find ANY documentation on this which makes me believe it is some tribal knowledge in the ARM community. 

 

Can anyone elaborate, point to or explain "where to find the documentation" or how this all works? Preferably, where the documentation is since it is kind of important to know exactly how the Zynq GP AXI interface works :)

 

Thanks in advance!

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7 Replies
Voyager
Voyager
2,806 Views
Registered: ‎06-24-2013

Re: How to create a burst transaction by a Zynq AXI GP Master?

Hey @jeff_king,

 

I created an AXI3-AXI4L protocol converter that assumes a well behaved Zynq single AXI3 transaction.

You mean, you created an incomplete protocol converter, as burst are part of the AMBA AXI specification.

 

bursts that show up periodically ... lock up the AXI bus because my converter doesn't support bursts ...

I would suggest to implement them or use an existing protocol converter which handles them correctly.

 

The problem is I don't know how the software guys create a burst (and they don't either)

The burst can be generated at different levels of the AXI bus/interconnect and of course in the CPU as well as the cache which typically will combine single access to larger blocks which will use bursts.

 

Can anyone elaborate, point to or explain "where to find the documentation" or how this all works?

The best source for AMBA AXI is the ARM documentation linked above.

For Xilinx related AXI IP, you might want to check PG059 and PG247.

For the features/limitations of the Zynq AXI interfaces the best place is the BFM.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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2,786 Views
Registered: ‎01-08-2012

Re: How to create a burst transaction by a Zynq AXI GP Master?

I've been in the same boat.

 

Look for wider transfers, e.g. 64 bit accesses if you have a 32 bit bus.

 

These may be hidden in library code, e.g. in functions such as memcpy() or memmove() or bcopy() etc.  These are usually implemented to be as fast as possible, and will typically use the widest possible transfer to reduce the number of bus accesses.  Failing that, it might be DMA related.

 

To debug, I suggest:

  1. modifying your converter so that it doesn't lock up the AXI when it receives a burst.  Instead, have it terminate with an error (I forget the exact signal name) so that you will be able to work out which transactions are causing the problem.  If done correctly, the (software) process that caused the issue should terminate with a bus error.
  2. modifying your converter to sniff the accesses with chipscope, then read them back over JTAG once your system has crashed.
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Scholar hbucher
Scholar
2,771 Views
Registered: ‎03-22-2016

Re: How to create a burst transaction by a Zynq AXI GP Master?

@jeff_king Go to Vivado HLS and create a simple top like

 

void top( uint32_t* mem ) 
{
#pragma HLS INTERFACE m_axi  port=mem  max_read_burst_length=16 max_write_burst_length=16
#pragma HLS INTERFACE s_axilite port=mem bundle=CFG
#pragma HLS INTERFACE s_axilite port=return bundle=CFG
    for ( uint32_t j=0; j<32; ++j ) mem[j] = j;
}

 This will create a minimal component that you can examine with detail. You can modify the burst parameters (or others) to see how the code changes. 

This will give you a baseline code that works and you can perhaps adapt it to your needs by adding logic to it. 

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Explorer
Explorer
2,753 Views
Registered: ‎12-06-2013

Re: How to create a burst transaction by a Zynq AXI GP Master?

@hpoetzl thank you for the links and corrections, however, I have the docs from ARM for the Zynq processor and the TRM is useless (in this case). Looking at the assembly instructions that are created we have only found that it is "likely" to introduce a burst if the reads/writes are back-to-back and ordered in such a way that the instructions "could" be put into a burst. I am looking for facts in documentation rather than responding to empirical results.

 

@allanherriman Your suggestion was how I found the problem in the first place, good call :) I just want to know (as well as our firmware guys) how to invoke a type of burst on purpose but the documentation is lacking. I am hoping someone else found a smoking gun as to how ARM implemented AXI packetizing so can make my protocol converter AXI3 compliant (for Zynq) and compact.

 

@hbucher Thanks for the suggestion!

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2,736 Views
Registered: ‎01-08-2012

Re: How to create a burst transaction by a Zynq AXI GP Master?

Perhaps this is a stupid question, but have you marked the section of address map where the FPGA resides as non-cacheable?  If not, accesses (either reading or writing) from the cache to the "memory" (FPGA in this case) will typically be in the form of large bursts, one cache line long.

 

This is probably set up correctly for you by the OS, unless you happen to be going "bare metal".

 

Allan

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Explorer
Explorer
2,701 Views
Registered: ‎12-06-2013

Re: How to create a burst transaction by a Zynq AXI GP Master?

@allanherriman, that section of address for the FPGA is marked as non-cacheable (not a stupid question :).

 

I added the burst read/write functionality to my AXI3-AXI4 protocol converter. However, in the spirit of "good engineering" I was hoping for an "absolute" response from Xilinx or a pointer to a white paper that discussed the finer details. This may be a better question for ARM. I have looked at a lot of posts and I have the feeling this was the question a lot of designer were trying to ask. Here are some of those posts here on the forums....I did not include what I found on the web.

 

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-Burst-on-Zynq-example/td-p/593180

 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/axi-slave-burst/m-p/373835/highlight/true#M441

 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/How-to-initiate-an-AXI-burst-transaction-with-Zynq-AXI-GP-M-port/m-p/793863/highlight/true#M16362

 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/AXI-Burst-configuration/m-p/424724/highlight/true#M1517

 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/ZedBoard-burst-read-and-write-through-GP-AXI/m-p/565304/highlight/true#M5699

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Visitor fdpo
Visitor
478 Views
Registered: ‎06-15-2016

Re: How to create a burst transaction by a Zynq AXI GP Master?

In my experience, you can generate read bursts with the ARM LDM instruction (need to write a little assembly code).  I tried to generate write bursts with STM, but it just resulted in a series of 2-word bursts.  You can also generate 2-word read or write bursts via 64 bit accesses (long long variables in C).

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