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Explorer
Explorer
3,714 Views
Registered: ‎04-23-2013

How to define SPI MOSI, MISO

Hello,

I have a Zynq design with an EMIO-connected SPI master interface.

Everything is working except that both IO ports are MOSI.

How do I get one of the io ports to be MISO?

 

The bd provides the following:

spi_0_io0_io : inout STD_LOGIC;
spi_0_io1_io : inout STD_LOGIC;
spi_0_sck_io : inout STD_LOGIC;
spi_0_ss1_o : out STD_LOGIC;
spi_0_ss2_o : out STD_LOGIC;
spi_0_ss_io : inout STD_LOGIC

 

 

I connect to EMIO in my contraints:

 

# SOM 92 = PIO52 = SPI_CLK
set_property PACKAGE_PIN L15 [get_ports {spi_0_sck_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_sck_io}]
set_property DRIVE 8 [get_ports {spi_0_sck_io}]
set_property SLEW SLOW [get_ports {spi_0_sck_io}]

# SOM 94 = PIO53 = SPI_MOSI
set_property PACKAGE_PIN L14 [get_ports {spi_0_io0_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_io0_io}]
set_property DRIVE 8 [get_ports {spi_0_io0_io}]
set_property SLEW SLOW [get_ports {spi_0_io0_io}]

# SOM 96 = PIO54 = SPI_MISO
set_property PACKAGE_PIN N16 [get_ports {spi_0_io1_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_io1_io}]
#set_property DRIVE 8 [get_ports {spi_0_io1_io}]
#set_property SLEW SLOW [get_ports {spi_0_io1_io}]


# SOM 98 = PIO55 = SPI_CSL0
set_property PACKAGE_PIN N15 [get_ports {spi_0_ss_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_ss_io}]
set_property DRIVE 8 [get_ports {spi_0_ss_io}]
set_property SLEW SLOW [get_ports {spi_0_ss_io}]

# SOM 102 = PIO56 = SPI_CSL1
set_property PACKAGE_PIN J14 [get_ports {spi_0_ss1_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_ss1_o}]
set_property DRIVE 8 [get_ports {spi_0_ss1_o}]
set_property SLEW SLOW [get_ports {spi_0_ss1_o}]

# SOM 104 = PIO57 = SPI_CSL2
set_property PACKAGE_PIN K14 [get_ports {spi_0_ss2_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_ss2_o}]
set_property DRIVE 8 [get_ports {spi_0_ss2_o}]
set_property SLEW SLOW [get_ports {spi_0_ss2_o}]

## PIO58,59 will eventually be CSL3,4
## SOM 106 = PIO58 = SPI_CSL3
#set_property PACKAGE_PIN G15 [get_ports {ol772_spi_ss_io[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {ol772_spi_ss_io[3]}]
#set_property DRIVE 8 [get_ports {ol772_spi_ss_io[3]}]
#set_property SLEW SLOW [get_ports {ol772_spi_ss_io[3]}]

 

## SOM 108 = PIO59 = SPI_CSL4
#set_property PACKAGE_PIN H15 [get_ports {ol772_spi_ss_io[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {ol772_spi_ss_io[4]}]
#set_property DRIVE 8 [get_ports {ol772_spi_ss_io[4]}]
#set_property SLEW SLOW [get_ports {ol772_spi_ss_io[4]}]

## PIO58,59 are temporarily CSL0,1 so they are present on J23
## SOM 106 = PIO58 = SPI_CSL0
set_property PACKAGE_PIN G15 [get_ports {spi_0_ss_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_ss_io}]
set_property DRIVE 8 [get_ports {spi_0_ss_io}]
set_property SLEW SLOW [get_ports {spi_0_ss_io}]

## SOM 108 = PIO59 = SPI_CSL1
set_property PACKAGE_PIN H15 [get_ports {spi_0_ss1_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_ss1_o}]
set_property DRIVE 8 [get_ports {spi_0_ss1_o}]
set_property SLEW SLOW [get_ports {spi_0_ss1_o}]

 

I initalize the SPI in SDK:

///////////////////////////////////////////////////////////////////////////
// Initialize SPI

// Initialize SPI Device
SpiConfig = XSpiPs_LookupConfig(XPAR_PS7_SPI_0_DEVICE_ID);
if (NULL == SpiConfig) return XST_FAILURE;

InitStatus = XSpiPs_CfgInitialize(&SpiInstance, SpiConfig, SpiConfig->BaseAddress);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

XSpiPs_Reset(&SpiInstance); // necessary??

SpiConfig->InputClockHz = XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ;

// Set the clock pre-scaler to 167MHz / 256 ~= 651kHz
InitStatus = XSpiPs_SetClkPrescaler(&SpiInstance, XSPIPS_CLK_PRESCALE_256);

// Perform a self-test to ensure that the hardware was built correctly. This defaults all options
InitStatus = XSpiPs_SelfTest(&SpiInstance);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Set the SPI device as a master, manual SS and auto start.
InitStatus = XSpiPs_SetOptions(&SpiInstance,
XSPIPS_MASTER_OPTION | XSPIPS_CLK_PHASE_1_OPTION);
// XSPIPS_MASTER_OPTION | XSPIPS_CLK_PHASE_1_OPTION | XSPIPS_FORCE_SSELECT_OPTION);
// XSPIPS_MASTER_OPTION | XSPIPS_CLK_ACTIVE_LOW_OPTION | XSPIPS_FORCE_SSELECT_OPTION);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Set the clock pre-scaler to 167MHz / 256 ~= 651kHz
InitStatus = XSpiPs_SetClkPrescaler(&SpiInstance, XSPIPS_CLK_PRESCALE_256);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Set the transfer delays = u8 DelayNss, u8 DelayBtwn, u8 DelayAfter, u8 DelayInit
// InitStatus = XSpiPs_SetDelays(&SpiInstance, 1, 2, 3, 40);
InitStatus = XSpiPs_SetDelays(&SpiInstance, 0, 0, 50, 100);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Enable the SPI device
XSpiPs_Enable(&SpiInstance);

 

Again.

Everything is working except that both IO ports are MOSI.

How do I get one of the io ports to be MISO?

 

Thanks,
Emmett

Tags (4)
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9 Replies
Explorer
Explorer
3,708 Views
Registered: ‎04-23-2013

Re: How to define SPI MOSI, MISO

To be more specific:

The entity provides the following ports:

entity block_design_wrapper is
port (

...

spi_0_io0_io : inout STD_LOGIC;
spi_0_io1_io : inout STD_LOGIC;
spi_0_sck_io : inout STD_LOGIC;
spi_0_ss1_o : out STD_LOGIC;
spi_0_ss2_o : out STD_LOGIC;
spi_0_ss_io : inout STD_LOGIC
);
end block_design_wrapper;

 

The component provides:

architecture STRUCTURE of block_design_wrapper is
component block_design is
port (

...

SPI_0_sck_i : in STD_LOGIC;
SPI_0_sck_o : out STD_LOGIC;
SPI_0_sck_t : out STD_LOGIC;
SPI_0_io0_i : in STD_LOGIC;
SPI_0_io0_o : out STD_LOGIC;
SPI_0_io0_t : out STD_LOGIC;
SPI_0_io1_i : in STD_LOGIC;
SPI_0_io1_o : out STD_LOGIC;
SPI_0_io1_t : out STD_LOGIC;
SPI_0_ss_i : in STD_LOGIC;
SPI_0_ss_o : out STD_LOGIC;
SPI_0_ss1_o : out STD_LOGIC;
SPI_0_ss2_o : out STD_LOGIC;
SPI_0_ss_t : out STD_LOGIC;

...

);
end component block_design;

 

Does this have anything to do with it?

Thanks,

Emmett

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Voyager
Voyager
3,673 Views
Registered: ‎06-24-2013

Re: How to define SPI MOSI, MISO

Hey @emmettbradford,

 

Everything is working except that both IO ports are MOSI.

That means that you connected the EMIOSPI0M* interfaces to both pins.

(or maybe EMIOSPI0M* and EMIOSPI1M*)

 

How do I get one of the io ports to be MISO?

By connecting the EMIOSPI0S* interface to one of them.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Explorer
Explorer
3,650 Views
Registered: ‎06-19-2015

Re: How to define SPI MOSI, MISO

Hi @emmettbradford

 

I too faced the similar issue. That was addressed in a guide, but i forgot where i have seen.

 

Any how, see the bold letters, this is how i remembered. 

 

spi_0_io0_io : inout STD_LOGIC; --> MOSI
spi_0_io1_io : inout STD_LOGIC; --> MISO

 

----------------------------------------------------------------------------------------------
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Thanks

Madhu

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Explorer
Explorer
3,628 Views
Registered: ‎04-23-2013

Re: How to define SPI MOSI, MISO

Hi Herbert,

Thanks for your reply.

Where do I find signals named EMIOSPI0S?

 

In the .bd, I "made external" the entire SPI port, and get the ports listed above.

The problem is that spi_0_io0_io, spi_0_io1_io are both MOSI.

 

I see that I can explicitly "make external" SCLK, MISO, MOSI in the .bd.

Is this how to accomplish what you are suggesting?

 

Thanks,
Emmett

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Explorer
Explorer
3,626 Views
Registered: ‎04-23-2013

Re: How to define SPI MOSI, MISO

Hi Madhu,

 

Thanks for your reply.

Isn't that what I did?

 

Thanks,

Emmett

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Explorer
Explorer
3,619 Views
Registered: ‎04-23-2013

Re: How to define SPI MOSI, MISO

Since the _i, _o, _t of the signals is port-mapped in the component, but not the entity ---

Should I be instantiating the component instead of the entity?

Thanks,

Emmett

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Voyager
Voyager
3,614 Views
Registered: ‎06-24-2013

Re: How to define SPI MOSI, MISO

Hey Emmet,

 

When you open the Elaborated Design, you should see something like this ...

schematic.png

I've highlighted the connections for MISO in blue and for MOSI in red.

If you look at the dark blue/red lines under Net Properties/Connectivity you will see the PS7 Cell Pins (EMIOSPI0M* and EMIOSPI0S*). Alternatively you can also expand the PS7 block further.

 

Note that in case you don't use the HDL Design Wrapper you need to connect the individual _I/_O/_T wires to an IOBUF yourself, either as instance or by inference.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
Explorer
Explorer
3,593 Views
Registered: ‎04-23-2013

Re: How to define SPI MOSI, MISO

Hi Herbert, Madhu,

I had it right initially.

The problem was an electrical connection on my board, which was the first thing I checked, or so I thought.

Thanks for all your help!
Emmett

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Highlighted
Voyager
Voyager
3,591 Views
Registered: ‎06-24-2013

Re: How to define SPI MOSI, MISO

You're welcome!

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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