10-11-2018 04:36 AM
I have emulated a Tensilica DSP on Artix7 FPGA on Zynq7000. While trying to access the softcore using Laughterbach, observed the logs such as following. Can you please let me know how to solve this issue in design? Is it something to do with design? Because the Tensilica DSP emulated on FPGA using a bit file generated after using RTL from Cadence, and Vivado tool for bit file generation.
CXTLX5Core: Core Domain is not powered
CXTLX5Core: Memory Domain is not powered
CXTLX5Core: Debug Domain is not powered
Attachment: Logs obtained from Laughterbach, Trace32.