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Observer reichardt
Observer
6,167 Views
Registered: ‎10-15-2008

Instable audio signals on the Zedboard

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Hi folks,

the existing i2s_ctrl IP that interfaces the audio-codec on the ZedBoard only supports polling but no interrupts.

 

As a result of the polling mechanism the audio output signal will not be read and generated with exactly the same period (That's what you can see on a scope). This leads to some noise disturbances as you can clearly hear in lab6 of the "Advanced Embedded System Design Workshop using Zynq".

I first tried to use a Timer interrupt but also this did not solve the problem, probably due to the fact that the time-base of the audio interface is different from the time-base of the timer.

 

So the only solution I see is to add an interrupt to the is2_ctrl IP.

 

Could anybody solve that problem already?

 

Thanks in advance

Juergen

 

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1 Solution

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Observer reichardt
Observer
8,188 Views
Registered: ‎10-15-2008

Re: Instable audio signals on the Zedboard

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the problem seams to be solved: It is NOT the polling mechanism but the PLL that is used within the ADAU 1761 codec which causes the signal jitter.

The solution:

1. in the ZYNQ device configure the clock-PLL to generate 12.5MHz MCLK output (Xilinx uses 10 MHz)

2. in the i2s_audio. c driver modify the AudioPllConfig() routine:

- send 0x01 to the R0_CLOCK_CONTROL register. This disables the internal PLL of the codec and uses the MCLK with divider 256 (i.e generates 48.828kHz sample rate) also enables the core clock.

- disable sending 0xF to the R0_CLOCK_CONTROL register at the end of the routine!

 

Thanks to the Xilinx employees who helped me to solve that problem!

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7 Replies
Xilinx Employee
Xilinx Employee
6,149 Views
Registered: ‎08-02-2011

Re: Instable audio signals on the Zedboard

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How about issuing an interrupt from the PL when a new sample is ready from the i2s controller?
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Observer reichardt
Observer
6,142 Views
Registered: ‎10-15-2008

Re: Instable audio signals on the Zedboard

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... thats actually the idea. It requires that the i2s_ctrl IP needs extension for interrupt support. But - what a pitty and nobody knows why - EDK 14.4 does no longer support interrupts in the CIP-wizard (Create and Import Peripheral). So I tried the example in AR_51138 but this has an "old-style" interface to the AXI4lite (slice direction is 0 to MAX-1). A lot of code rewriting is necessary in regions where Xilinx explicitely states "DONT MODIFY".

 

I'm surprised that no other person noticed that problem with the audio-interface before

 

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Teacher muzaffer
Teacher
6,132 Views
Registered: ‎03-31-2012

Re: Instable audio signals on the Zedboard

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are you using the axi_iic block in Vivado? that has an interrupt output. If not I am not sure what i2s_ctrl this is. Does it not have a data ready signal output? You should be able to connect it to the interrupt input of your processor directly.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Observer reichardt
Observer
6,125 Views
Registered: ‎10-15-2008

Re: Instable audio signals on the Zedboard

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I'm (still) using EDK 14.4 started via PlanAhead (not yet Vivado). The i2s_ctrl IP has the task of serializing and deserializing the audio datastream from/to the audio codec. It has port interfaces like BCLK, LRCLK, SDO, SDI to the audio codec. The original IP as a status register which indicates new data available but it is my feeling that it needs an interrupt port which is driven by new data available...

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Observer reichardt
Observer
8,189 Views
Registered: ‎10-15-2008

Re: Instable audio signals on the Zedboard

Jump to solution

the problem seams to be solved: It is NOT the polling mechanism but the PLL that is used within the ADAU 1761 codec which causes the signal jitter.

The solution:

1. in the ZYNQ device configure the clock-PLL to generate 12.5MHz MCLK output (Xilinx uses 10 MHz)

2. in the i2s_audio. c driver modify the AudioPllConfig() routine:

- send 0x01 to the R0_CLOCK_CONTROL register. This disables the internal PLL of the codec and uses the MCLK with divider 256 (i.e generates 48.828kHz sample rate) also enables the core clock.

- disable sending 0xF to the R0_CLOCK_CONTROL register at the end of the routine!

 

Thanks to the Xilinx employees who helped me to solve that problem!

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Visitor fpgarolf
Visitor
4,927 Views
Registered: ‎09-20-2014

Re: Instable audio signals on the Zedboard

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I wonder if this will lead to valid S/PDIF frequencies. Does this work with external quipment?

 

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Newbie reg-audio
Newbie
4,757 Views
Registered: ‎10-23-2014

Re: Instable audio signals on the Zedboard

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Hello Everybody,

 

I'm currently experiencing similar problems. Disabling the codc's PLL did in fact improve the output Signal, but there are still intermodulation products visible.

Is that the result of the Base Sampling Frequency not being exactly 48kHz as the codec might expect?

As I interpret this problem, the ADAU's PLL simply doesn't work properly. Is Analog aware of that? Is there a chance for getting a replacement?

 

Greetings

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