I want to build a project that contains AXI chip2chip master and slave both. (Selected IO SDR, connected to each other directly)
However, during the implementation stage, I got a message below and failed.
Internal Data Exception: Site type arc id '24' out of range. The pips vector has 11 elements. The site type name is 'BITSLICE_RX_TX'
Isn't it possible to build an hardware that contains both AXI chip2chip master and slave?
Or, Is there any solution for this problem?
My vivado version is 2017.4 version and run on Windows 10.