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Observer ru551n
Observer
9,596 Views
Registered: ‎02-09-2010

MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

Hello,

 

Im having issues getting through the translate step when using the new MCS IP-core in 13.4.

 

I have project navigator open, generate and instantiate the MCS in top level.

Then I run the microblaze_mcs_setup.tcl script via the tcl console.

 

When I then try to perform Implement on the project, I get the following error (copied from console).

 

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/project/top.xst" -ofn "C:/project/top.syr"
Reading design: top.prj
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\project\ipcore_dir\microblaze.vhd" into library work
Parsing VHDL file "C:\project\clk_gen.vhd" into library work
Parsing entity <clk_gen>.
Parsing architecture <xilinx> of entity <clk_gen>.
Parsing VHDL file "C:\project\top.vhd" into library work
Parsing entity <top>.
Parsing architecture <Behavioral> of entity <top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <top> (architecture <Behavioral>) from library <work>.

Elaborating entity <clk_gen> (architecture <xilinx>) from library <work>.
WARNING:HDLCompiler:89 - "C:\project\top.vhd" Line 51: <microblaze> remains a black-box since it has no binding entity.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <top>.
    Related source file is "c:/project/top.vhd".
    Summary:
	no macro.
Unit <top> synthesized.

Synthesizing Unit <clk_gen>.
    Related source file is "c:/project/clk_gen.vhd".
    Summary:
	no macro.
Unit <clk_gen> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <ipcore_dir/microblaze.ngc>.
Loading core <microblaze> for timing and area information for instance <inst_microblaze>.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 8.
WARNING:Xst:387 - The KEEP property attached to the net <inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[4].local_sel_n> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[3].local_sel_n> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[2].local_sel_n> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[1].local_sel_n> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[0].local_sel_n> may hinder timing optimization.
   You may achieve better results by removing this property
INFO:Xst:2260 - The FF/Latch <U0/ilmb/POR_FF_I> in Unit <inst_microblaze> is equivalent to the following FF/Latch : <U0/dlmb/POR_FF_I> 
INFO:Xst:2260 - The FF/Latch <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[31].fdr_i> in Unit <inst_microblaze> is equivalent to the following 31 FFs/Latches : <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[30].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[29].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[28].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[27].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_c
trl_I1/cipr_rd_dff_all[26].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[25].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[24].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[23].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[22].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[21].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[20].fdr_i>
   <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[19].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[18].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[17].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[16].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[15].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[14].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[13].f
dr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[12].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[11].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[10].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[9].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[8].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[7].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[6].fd
r_i>
   <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[5].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[4].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[3].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[2].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[1].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[0].fdr_i> 
INFO:Xst:2260 - The FF/Latch <U0/ilmb/POR_FF_I> in Unit <inst_microblaze> is equivalent to the following FF/Latch : <U0/dlmb/POR_FF_I> 
INFO:Xst:2260 - The FF/Latch <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[31].fdr_i> in Unit <inst_microblaze> is equivalent to the following 31 FFs/Latches : <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[30].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[29].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[28].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[27].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_c
trl_I1/cipr_rd_dff_all[26].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[25].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[24].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[23].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[22].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[21].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[20].fdr_i>
   <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[19].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[18].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[17].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[16].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[15].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[14].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[13].f
dr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[12].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[11].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[10].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[9].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[8].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[7].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[6].fd
r_i>
   <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[5].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[4].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[3].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[2].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[1].fdr_i> <U0/iomodule_0/IOModule_Core_I1/intr_ctrl_I1/cipr_rd_dff_all[0].fdr_i> 

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                              | Clock buffer(FF name)                                                                                                  | Load  |
------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-------+
sysclk_p_i                                                                                | DCM_SP:CLKDV                                                                                                           | 599   |
inst_microblaze/U0/Debug.mdm_0/drck_i                                                     | BUFG                                                                                                                   | 205   |
inst_microblaze/U0/Debug.mdm_0/update                                                     | NONE(inst_microblaze/U0/microblaze_I/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/command_reg_0)| 39    |
inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/valid_Write| NONE(inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DFF[31].PLBv46_rdBus_FDRE)              | 34    |
------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 10.194ns (Maximum Frequency: 98.097MHz)
   Minimum input arrival time before clock: 8.364ns
   Maximum output required time after clock: 8.703ns
   Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc SP601_RevC_annotated_master_ucf_8-28-09.ucf -p xc6slx16-csg324-2 top.ngc top.ngd -bm "ipcore_dir/microblaze.bmm"

Command Line: C:\Xilinx\13.4\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -sd ipcore_dir -nt timestamp -uc
SP601_RevC_annotated_master_ucf_8-28-09.ucf -p xc6slx16-csg324-2 top.ngc top.ngd
-bm ipcore_dir/microblaze.bmm

Reading NGO file "C:/project/top.ngc" ...
Loading design module "ipcore_dir/microblaze.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"SP601_RevC_annotated_master_ucf_8-28-09.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...

Done...

Processing BMM file "ipcore_dir/microblaze.bmm" ...
ERROR:NgdBuild:989 - Failed to process BMM information ipcore_dir/microblaze.bmm

Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[31].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[30].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[29].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[28].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[27].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[26].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[25].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/PLB_Interconnect.PLBv46_rdDBus_DF
   F[24].PLBv46_rdBus_FDRE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'inst_microblaze/U0/Debug.mdm_0/MDM_Core_I1/TX_Buffer_Empty_FDRE' has
   unconnected output pin

INTERNAL_ERROR:(null):45 - Memory allocation leak of 60 bytes at 0x05D0D81C for a 'AddressMappingType' record.
    Total memory in use at allocation was 19779 bytes.
    Source file "BmmUtils.c", line number 3050.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 42 bytes at 0x05D2803C for a StrNew.
    Total memory in use at allocation was 19839 bytes.
    Source file "BmmUtils.c", line number 3055.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 52 bytes at 0x0564BCB0 for a 'AddressMapType' record.
    Total memory in use at allocation was 19881 bytes.
    Source file "BmmUtils.c", line number 2568.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 24 bytes at 0x05D27FE0 for a 'symbol_context' record.
    Total memory in use at allocation was 19933 bytes.
    Source file "SymbolUtils.c", line number 516.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 22 bytes at 0x0578BA48 for a StrDup.
    Total memory in use at allocation was 19957 bytes.
    Source file "BmmUtils.c", line number 2581.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 8 bytes at 0x06B86148 for a 'DataFileNameListType' record.
    Total memory in use at allocation was 19979 bytes.
    Source file "data2bramCore.c", line number 3535.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 12 bytes at 0x06B861AC for a 'AddressSpaceLinkType' record.
    Total memory in use at allocation was 19987 bytes.
    Source file "BmmUtils.c", line number 2287.


INTERNAL_ERROR:(null):45 - Memory allocation leak of 60 bytes at 0x06EB5F0C for 'void *' data.
    Total memory in use at allocation was 19999 bytes.
    Source file "D2BUtil_Data2Bram.c", line number 722.


Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   9

Total REAL time to NGDBUILD completion:  4 sec
Total CPU time to NGDBUILD completion:   4 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "top.bld"...

Process "Translate" failed

 I have followed all the steps and verified everything according to http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ds865_microblaze_mcs.pdf

 

In the MCS core, I have selected the MDM debug module and 8 kB memory.

 

My goal is to generate a bitstream, which I can download to my SP601 board and upload some code using xmd and the JTAG cable.

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1 Solution

Accepted Solutions
Observer ru551n
Observer
11,989 Views
Registered: ‎02-09-2010

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

I solved the problem. 

Turns out you must specify "path to core instance" the same as your instance name in the HDL design, as the scripts use this to generate the .bmm files.

Is this working as intended? Seems reasonable to me though :-)

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7 Replies
Xilinx Employee
Xilinx Employee
9,571 Views
Registered: ‎08-06-2007

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

Hi,

 

There seems to some issue with the automatically generated .bmm file according to the console output.

 


Processing BMM file "ipcore_dir/microblaze.bmm" ... ERROR:NgdBuild:989 - Failed to process BMM information ipcore_dir/microblaze.bmm

 

Please post the contents of the .bmm file so I can check if the contents is ok.

You can also try to regenerate the MCS using Coregen to see if this would create a correct .bmm file

 

Göran

 

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Observer ru551n
Observer
11,990 Views
Registered: ‎02-09-2010

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

I solved the problem. 

Turns out you must specify "path to core instance" the same as your instance name in the HDL design, as the scripts use this to generate the .bmm files.

Is this working as intended? Seems reasonable to me though :-)

0 Kudos
Xilinx Employee
Xilinx Employee
9,541 Views
Registered: ‎08-06-2007

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

Hi,

 

Yes, the "path to core instance" is the path in your design which would then include your instance name.

It's needed to be able to have the correct path name for the brams in the generate .bmm file.

 

Göran

Visitor xiaowenkun
Visitor
9,204 Views
Registered: ‎10-01-2010

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

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Good, I have been looking for the solution of this problem for a long time.

Yes, the instance name in hdl must same as the name of "Instance Hierarchial Design Name" in IP core generator wizard.

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7,167 Views
Registered: ‎11-19-2013

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

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Hi Goran,

I do not understand how to fix this problem.

I am working on MCS and i have given name mcs_ip...to the microblaze ip. i am using 14.4 webpack. i could add mcs_ip.xco fiel to my project and then instantiate it in my top vhdl file. somethinhg like

mcs1_ip: mcs_ip

 port map(

---

-- port names and links--

);

 

but still getting the memory leak errors.

can you help how to solve it.

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Xilinx Employee
Xilinx Employee
7,159 Views
Registered: ‎08-06-2007

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

Hi,

 

Have you read the implementation flow in the MCS documentation?

http://www.xilinx.com/support/documentation/sw_manuals_j/xilinx14_4/pg048-microblaze-mcs.pdf

 

- Chapter 6 is when using the ISE flow

- page 44 has a diagram on the design flow.

- page 35 talks about the "Instance Hierarchical Design Name" which the path from your top level to your instanciation of the MCS.
ex.  If you instanciate MCS in top-level at sub_level_0/sub_level_1 as mcs_ip, you need to use "sub_level_0/sub_level_1/mcs_ip" as the "Instance Hierarchical Design Name" when generating the MCS core.

 

Göran

 

 

 

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Newbie diesel12
Newbie
6,181 Views
Registered: ‎07-11-2014

Re: MCS (Micro Controller System) issue - Translate (BRAM initialization) problem

Jump to solution

ISE webpack 14.7, I also have the same issue, and cant seem to understand fully on how to solve it

 

I followed Jim Duckworth's tutorial to the letter, and read the MCS documentation, makeing sure that mcs_0 was the name used to create the IP, and the same name was used to instantiate the core in the hdl.

 

for file structure I have blazetest\ipcore_dir\mcs_0 as a directory structure after the ip was generated

 

at the ipcore_dir level there is a mcs_0.bmm file.   here is part of its contents

BUS_BLOCK
        blazetest\ipcore_dir\mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[0].RAMB16_S4_1 [31:28] INPUT = mcs_0.lmb_bram_0.mem;

 

In the mcs_0 folder there are 3 files

 

mb_bootloop_le.elf

microblaze_mcs_setup.tcl

system_template.tcl

 

This is what is in the hdl file for instantiation

 

microblaze_mcs : mcs_0

 

Any help is appreciated

 

Mike

 

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