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4,132 Views
Registered: ‎11-01-2016

MPSoC PS PCIe usage from PL

Hi,

 

I have an application where i need to stream high bandwidth data using PCIe from the MPSoC(Configured as RC or RP) but without using CPU.

Unfortunatly the first MPSoC devices (such as the ES1 on my ZCU102) do not include a PL PCIe block but only the PS PCIe.

Is it theoreticaly possible to have the PL access the PS PCIe through one of the AXI ports (AXI_HP or AXI_HPC) via the Core Switch ?

Can i have the APU setup the PCIe using the normal Linux bringup and then have the PL perform writes to the PCIe registers

I have already reviewed the TRM, Forums, example designs and XAPP1289 but have not found any PL references.

 

Thanks,

Gilad

 

 

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Xilinx Employee
Xilinx Employee
4,100 Views
Registered: ‎08-01-2008

Re: MPSoC PS PCIe usage from PL

Check these user guide if you have not done yet
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf
Thanks and Regards
Balkrishan
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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: MPSoC PS PCIe usage from PL

I haven't gone through us+ TRM fully yet but this is possible in current zynq ie PL can access the PS controllers using some of the PL master ports. I can't imagine why it would be removed in us+ parts.
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