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Observer wolff000
Observer
1,684 Views
Registered: ‎08-10-2012

MPSoC power management questions

Hello!  I have a few questions about the MPSoC power management system as follows.  My questions all relate to a system in which the RPU runs continuously, while the APU is brought up and down as needed.  This configuration is described at the top of the "deep sleep with periodic wakeup" wiki page:

http://www.wiki.xilinx.com/ZU%EF%BC%8B+Example+-+Deep+Sleep+with+Periodic+Wake-up

 

Here are my questions:

 

1) How does the FSBL work in this configuration?  Specifically:

- do both the RPU and the APU need to run their own copies of the FSBL, and if so how do you keep the two versions from stomping on each other for common PSU settings?

- I noticed that the Power Advantage Tool BIF file only includes an APU FSBL, but I'm not clear how this works.  Specifically, what happens when the APU resumes?  Won't the FSBL run again and re-initialize the PSU, causing problems with interfaces that are already being used by the RPU?

 

2) In the examples that you provide, the APU self-suspends, after which the PMU can shut off the full FPD power domain (i.e. NODE_FPD in PMUFW pm_defs.h).  However, the Power Advantage Tool also provides the ability to disable the ZCU102 power supplies for the FPD.  Questions:

- can you achieve a significant power savings by shutting off power externally versus only having the PMU shut off the power domain?

- can you resume from this configuration, i.e. will the DDR remain in self-refresh mode with the contents preserved even after the FPD and APU are re-enabled?  Or will the DDR controller get reinitialized by the FSBL and cause the memory contents to be lost?

 

3) The MPSoC TRM describes how PMU GPIO1 line 0 can be used to control FPD power and line 1 can be used to control PL power (Table 6-10 in UG1085 v1.5).  And I see on the ZCU102 schematic that these signals (MIO32/33 respectively) are connected to the MSP430.  However:

- I could not find any use of these signals in the PMUFW (2016.4 version)

- the MSP430 code provided with the Power Advantage Tool is configured to respond to transitions on the corresponding I/O lines -- see DoPmu() in gpio.c.  However, the PMUFW version provided with the Power Advantage Tool also does not appear to use MIO32/33

- what am I missing here?

 

Thank you very much for your help with these questions!

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1 Reply
Xilinx Employee
Xilinx Employee
1,380 Views
Registered: ‎06-15-2017

Re: MPSoC power management questions

1) In the Suspend / Resume case, FSBL is not run again after boot.

 

2) The power saving between the two methods is identical, as both ways fully turn off the power rails at the PMIC. The idea is to retain the DDR contents after the FPD Off Suspend to DDR. There is a demo version of this in the 2017.1 version of the Power Advantage Tool. This feature is currently available on a limited basis... Please see your FAE for more information on this feature.

http://www.wiki.xilinx.com/Zynq+UltraScale%EF%BC%8B+MPSoC+Power+Advantage+Tool+part+1+-+Introduction+to+the+Power+Advantage+Tool

 

3) The PMUFW does not have code to control these GPIO's, rather they are in the PMU ROM. (e.g. PMUFW calls the ROM handler to control MIO32 (i.e. XpbrServHndlrTbl[XPBR_SERV_EXT_PWRDNFPD]).

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