08-02-2015 06:17 PM
I'm using a Spartan6 with ISE and XPS/EDK. It's an AXI design that has a large number of peripherals (mostly custom IP) on AXI4LITE.
Currently each of the custom peripherals has its own separate AXI4LITE bus interface (using the axi_lite_ipif core) and separate software driver libraries. This seems good for hierarchical design and reusability, but I'm not sure if it's the ideal in terms of FPGA performance.
Another option that I've considered is to make "one peripheral to rule them all" which either maps AXI4LITE to Wishbone or similar or just directly ties up all the "user_logic"s of my existing peripherals and presents a unified front to the EDK. This seems bad for hierarchy and complex to code but might be better for performance?
Is one of these approaches better than the other for the FPGA design? In particular here I'm referring to the area required by the design and the ease of meeting timing. As it is the current separate-peripherals design takes about ten hours just to build, and can at times be a pain to get to pass timing, and I'm wondering if making the effort to merge the peripherals would make this better, worse, or not really change much. (I'm open to ideas on restructuring the internals but the ship has sailed on changing pin assignments.)
08-02-2015 07:10 PM - edited 08-02-2015 07:39 PM
Related question is whether it's better to design a core with 16 inputs and 8 registers, and then instantiate 2 of these at the top level, or to make a core with 32 inputs and 16 registers and instantiate only one. Or whether that doesn't really make any difference. (Again assume for the purposes of discussion that the two separate cores are "better" from a design aesthetic perspective; the question here is one of compile/timing/area performance.)
08-03-2015 02:46 PM
08-09-2015 06:05 PM