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Explorer
Explorer
6,593 Views
Registered: ‎03-22-2014

Max Frequency of PL on ZedBoard ?

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hello,

 

i work on zedboard as an embedded solution for a real time application

 

during my research and work, i can't found a clear documentation about the max frequency of the PL !!!

 

some time i found a tutorial whtich use PL, told that the max frequency is 250 Mhz , but there is no possible to fix the clock for this value,  just 100 Mhz is the value used in many tutorial !!!

in others cases, i got a magic answer from other support team ( on other project , hey told me that there is no max frequency ?

any idea

 

thank you

My blog : www.xilinx-video.blogspot.com
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1 Solution

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Community Manager
Community Manager
9,584 Views
Registered: ‎06-14-2012

Re: Max Frequency of PL on ZedBoard ?

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Just to add some more perspective.

 

PL comprises of all FPGA logic. Its basically similar to a soft Ip where the max frequency will really depend on how the design has been implemented.For example, The Zynq PS AXI interfaces are able to close timing above 200 MHz, but may require assistance in ISE-based tools.In ISE Design Suite tools, the Zynq PS AXI interfaces respond very well to basic floorplanning of the axi_interconnect connecting to the right side of the PS7 primitive.

This is just an example. Hope it helps.

 

Regards

Sikta

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4 Replies
Xilinx Employee
Xilinx Employee
6,588 Views
Registered: ‎08-02-2007

Re: Max Frequency of PL on ZedBoard ?

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Hi,

 

The maximum frequency of the PL depends on the design and the components used in the it.

 

We should think about it similar to "what is the maximum frequency of the design?"

 

--Hem

 

 

 

 

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Explorer
Explorer
6,570 Views
Registered: ‎03-22-2014

Re: Max Frequency of PL on ZedBoard ?

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hello

 

 

i think there is 4 clock come from the PS to PL, so the max frequency will be fixed or generated from the PS ? 

 

 

My blog : www.xilinx-video.blogspot.com
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Moderator
Moderator
6,561 Views
Registered: ‎04-17-2011

Re: Max Frequency of PL on ZedBoard ?

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The PL has its own clock management generation and distribution features and also receives four
clock signals from the clock generator in the PS. 
The four clocks that are generated by the PS are completely asynchronous to each other with no
relationship to other PL clocks.
And, the maximum frequency of PL cannot be determined with these 4 FCLK's.

Regards,
Debraj
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Community Manager
Community Manager
9,585 Views
Registered: ‎06-14-2012

Re: Max Frequency of PL on ZedBoard ?

Jump to solution

Just to add some more perspective.

 

PL comprises of all FPGA logic. Its basically similar to a soft Ip where the max frequency will really depend on how the design has been implemented.For example, The Zynq PS AXI interfaces are able to close timing above 200 MHz, but may require assistance in ISE-based tools.In ISE Design Suite tools, the Zynq PS AXI interfaces respond very well to basic floorplanning of the axi_interconnect connecting to the right side of the PS7 primitive.

This is just an example. Hope it helps.

 

Regards

Sikta

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