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Explorer
Explorer
2,212 Views
Registered: ‎07-14-2014

Microblaze DDR3 Execution Failing

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Hi all,

 

I'm in need of some advice or suggestions as I've got a bit of a problem with microblaze not executing code from DDR3.

 

I have 2 designs, both built on the same version of the tool (2016.1), both using identical CPU settings for cache etc, both tested on the same hardware with the same bootloader code. One of them executes code from DDR3 after the bootloader completes, the other doesn't.

 

I have captured some ILA traces for each instance to try and work out what is going on, if it helps.

 

The working design (ICP60X2) seems to complete the bootloader, and then begin reading instructions from the DDR3 using the IC port. PC (Program counter is stable for long periods during these reads (as I would sort of expect when doing reads from DDR3 as they are not going to be single cycle. (see sample 973 onwards)

 

The failing example (ICP60) also completes the bootloader in the same way and also begins to read data via the IC port. However, the PC during this is effectively stuck in a very tight loop, running 2 instructions from the start of the DDR3 memory which causes it to jump back to the start of DDR3 memory (See sample 1020 onwards). I'm at a loss to explain the difference in the behaviour.

 

On the working design the OF_PIPERUN signal (which I believe controls the instruction decode pipeline) stays inactive for long periods (similar to the PC), but the failing design seems to keep running instructions.

 

I'm not even sure where the instructions for this tight loop are coming from since the bootloader checks the first few memory locations after it has loaded them and they seem to contain values that are correct for the code in the elf but are not what is executing.

 

Right now I'm stumped as to what is causing this. It seems like something in the CPU is not doing what it should be but I can't tell what it is from the information I have.

 

I have attached the 2 ILA files so you can see what I am going on about.

 

Any suggestions would be appreciated as to what magic incantations I need to use as at the moment it seems like the CPU is not behaving properly for some reason in one of the designs.

 

Regards

 

Simon

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Explorer
Explorer
4,120 Views
Registered: ‎07-14-2014

Re: Microblaze DDR3 Execution Failing

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FYI

 

Managed to fix this now. After comparing the 2 BD TCL files for the 2 designs (not a simple process as although one design had removed a large number of blocks it had also added a couple more, making it hard work for the diff tool).

 

To cut a long story short I noticed that there was a CONFIG.C_MASK property being set in the dlmb_bram_if_cntlr and ilmb_bram_if_cntlr for the design that didn't work.

 

Checking the LMB interface on the block diagram indicated that the SLMB setting for both ILMB and DLMB was set to manual. Changing this to automatic and rebuilding seems to have cured the problem.

 

Not sure how/why this got changed to manual but it appears to have been that way in the design since it was started in 2014.2. Until recently the CPU had been running with 1MB of BRAM but this was causing us issues in P&R now the FPGA was filling up, so we opted to run from DDR3 and reduce BRAM to 64KB. The SLMB settings seem to have caused the CPU to decide that the start of DDR3 address actually resided in BRAM and just decoded the reset vector, which pointed to the start of DDR3 which was decoded as the reset vector etc, etc...

 

Hopefully this post might help someone else in future

 

Regards

 

Simon

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1 Reply
Highlighted
Explorer
Explorer
4,121 Views
Registered: ‎07-14-2014

Re: Microblaze DDR3 Execution Failing

Jump to solution

FYI

 

Managed to fix this now. After comparing the 2 BD TCL files for the 2 designs (not a simple process as although one design had removed a large number of blocks it had also added a couple more, making it hard work for the diff tool).

 

To cut a long story short I noticed that there was a CONFIG.C_MASK property being set in the dlmb_bram_if_cntlr and ilmb_bram_if_cntlr for the design that didn't work.

 

Checking the LMB interface on the block diagram indicated that the SLMB setting for both ILMB and DLMB was set to manual. Changing this to automatic and rebuilding seems to have cured the problem.

 

Not sure how/why this got changed to manual but it appears to have been that way in the design since it was started in 2014.2. Until recently the CPU had been running with 1MB of BRAM but this was causing us issues in P&R now the FPGA was filling up, so we opted to run from DDR3 and reduce BRAM to 64KB. The SLMB settings seem to have caused the CPU to decide that the start of DDR3 address actually resided in BRAM and just decoded the reset vector, which pointed to the start of DDR3 which was decoded as the reset vector etc, etc...

 

Hopefully this post might help someone else in future

 

Regards

 

Simon

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