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Observer mohamd17
Observer
1,809 Views
Registered: ‎01-14-2017

Microzed 7020 overflow IOBs : Please What I can do in this case ?


*** Running vivado
with args -log keccak.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source keccak.tcl -notrace


****** Vivado v2016.3 (64-bit)
**** SW Build 1682563 on Mon Oct 10 19:07:27 MDT 2016
**** IP Build 1681267 on Mon Oct 10 21:28:31 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source keccak.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 70 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'keccak' is not ideal for floorplanning, since the cellview 'keccak' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-479] Netlist was created with Vivado 2016.3
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 481.816 ; gain = 271.852
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.895 . Memory (MB): peak = 491.402 ; gain = 9.586
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task
Implement Debug Cores | Checksum: cf7f55a6

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: cf7f55a6

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.819 . Memory (MB): peak = 995.035 ; gain = 0.000

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant propagation | Checksum: cf7f55a6

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 995.035 ; gain = 0.000

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 0 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 3 Sweep | Checksum: cf7f55a6

Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 995.035 ; gain = 0.000

Phase 4 BUFG optimization
INFO: [Opt 31-12] Eliminated 0 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 4 BUFG optimization | Checksum: cf7f55a6

Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 995.035 ; gain = 0.000

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 995.035 ; gain = 0.000
Ending Logic Optimization Task | Checksum: cf7f55a6

Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 995.035 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: cf7f55a6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 995.035 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 995.035 ; gain = 513.219
INFO: [Common 17-1381] The checkpoint 'C:/Users/Simo/Test_keccak/Test_keccak.runs/impl_2/keccak_opt.dcp' has been generated.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Simo/Test_keccak/Test_keccak.runs/impl_2/keccak_drc_opted.rpt.
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 995.035 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 995.035 ; gain = 0.000

Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (134) is greater than number of available sites (125).
The following Groups of I/O terminals have not sufficient capacity:
ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 13 | 25 | 0 | | | | | | |
| 34 | 50 | 0 | | | | | | |
| 35 | 50 | 0 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 125 | 0 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 63e22274

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1018.289 ; gain = 23.254
Phase 1 Placer Initialization | Checksum: 63e22274

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1018.289 ; gain = 23.254
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 63e22274

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1018.289 ; gain = 23.254
INFO: [Common 17-83] Releasing license: Implementation
37 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Tue Apr 18 20:04:01 2017...

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3 Replies
Scholar austin
Scholar
1,798 Views
Registered: ‎02-27-2008

Re: Microzed 7020 overflow IOBs : Please What I can do in this case ?

1.  Use fewer IO pins, or

2.  Choose a device with sufficient IO.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer mohamd17
Observer
1,756 Views
Registered: ‎01-14-2017

Re: Microzed 7020 overflow IOBs : Please What I can do in this case ?

Thank you for your response,

That seems logical to me.
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Observer mohamd17
Observer
1,730 Views
Registered: ‎01-14-2017

Re: Microzed 7020 overflow IOBs : Please What I can do in this case ?

Hi evryone !

 

How can I split the 64-bit Din register into two 32-bit registers ?

Then by doing this, can I get rid of the overflow of IOB ?

 

Here is my entity :

 

entity keccak is

port (
clk : in std_logic;
rst_n : in std_logic;
init : in std_logic;
go : in std_logic;
absorb : in std_logic;
squeeze : in std_logic;
din : in std_logic_vector(63 downto 0);
ready : out std_logic;
dout : out std_logic_vector(63downto 0));

end keccak;

 

Thank you 

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