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Newbie nallkar
Newbie
170 Views
Registered: ‎01-17-2019

More detailed information needed for silicon issue in document, Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320 (v1.0) July)

Hi,

Can some one provide more detailed information or link to information for silicon issue in document, Isolation Methods in
Zynq UltraScale+ MPSoCs, XAPP1320 (v1.0).

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The XMPU and XPPU have a silicon issue related to the locking of the registers and use of
interrupts. The issue is discussed in Xilinx Answer 66183. The solution used in the reference
design is to use the PMU subsystem for handling XMPU and XPPU events.

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66183 point to https://www.xilinx.com/support/answers/66183.html. This does directly seem to contain relevant information, or I cannot find it from there.

 

--Kari

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2 Replies
Xilinx Employee
Xilinx Employee
94 Views
Registered: ‎09-04-2012

Re: More detailed information needed for silicon issue in document, Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320 (v1.0) July)

The XAPP is being revised.

The XPPU/XMPU silicon errata mentioned was for ES1 silicon. There are no issues with production silicon which is the reason why you cannot find more information on the AR.

 

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Newbie nallkar
Newbie
75 Views
Registered: ‎01-17-2019

Re: More detailed information needed for silicon issue in document, Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320 (v1.0) July)

Thank you for information.

 

--Kari

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