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Participant vaibhawaxilinx
Participant
577 Views
Registered: ‎04-06-2011

No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

Hi 

I am using Zynq ultra-scale+ MPSoC ( xczu17eg-ffvc1760-2-e) based board from HiTech Global. I am trying to access PL DDR4 memory with PS DMA ( ZDMA).  MIG block is connected with HPM0_FPD master port. 

I can see write and read transaction when I am using memcpy function. However, if I use ZDMA example code to write and read to PL DDR, I can only see read transaction. No write transaction is seen.  Same happens If I use local BRAM. 

 

Please help me to know if I miss any configuration.

 

BR

Vab 

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6 Replies
Participant vaibhawaxilinx
Participant
423 Views
Registered: ‎04-06-2011

Re: No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

Not a single reply yet.

BR

Vaibhawa

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Voyager
Voyager
400 Views
Registered: ‎02-01-2013

Re: No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

What do you mean you can "see write and read transaction[s]"? Are you using an ILA to observe AXI transfers in the PL?

One thing I learned years ago about Zynq is: don't use PS DMA; use AXI DMA in PL--especially for PL-to-PL transfers.

-Joe G.

 

 

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Participant vaibhawaxilinx
Participant
385 Views
Registered: ‎04-06-2011

Re: No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

Hi Joe 

Yes. I am using ILA to observe transactions.

I agreed on your point using AXI DMA but in my  case I need to transfer large data between PS-DDR to PL-DDR. 

Hope I made clear this time. 

Do you have any suggestion on above ?

Thanks 

Vaib

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Voyager
Voyager
370 Views
Registered: ‎02-01-2013

Re: No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

Same suggestion: try using a PL-based AXI DMA instead of PS-based DMA. The former is capable of retrieving data from the PS and PS-DDR, too.

-Joe G.

 

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Xilinx Employee
Xilinx Employee
272 Views
Registered: ‎09-01-2014

Re: No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

ZDMA has a read-only or write-only mode. do you set the mode correctly?
Please check the wiki page for the example design
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841725/ZynqMP+DMA+Standalone+driver
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Xilinx Employee
Xilinx Employee
235 Views
Registered: ‎10-04-2016

Re: No write transaction seen on M_AXI_HPM0_FPD using PS DMA in Zynq ultra-scale+ MPSoC

Hi @vaibhawaxilinx,

I think the best place to start is to verify that you set up the destination address correctly. Are you using the ZDMA in scatter gather or simple mode? If you are using simple mode, can you dump the registers for the channel you are using? What is the destination address set to?

If you are using scatter gather mode, can you dump the contents of the first buffer descriptor?

The other thing to look out for is whether the ZDMA is reporting any errors. Check the ZDMA_CH_ISR as it reports a variety of errors.

Please consult UG1087 to identify the address of these registers.

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

Regards,

Deanna

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