11-02-2018 11:16 AM
I am using Zynq ultra-scale+ MPSoC ( xczu17eg-ffvc1760-2-e) based board from HiTech Global. I am trying to access PL DDR4 memory with PS DMA ( ZDMA). MIG block is connected with HPM0_FPD master port.
I can see write and read transaction when I am using memcpy function. However, if I use ZDMA example code to write and read to PL DDR, I can only see read transaction. No write transaction is seen. Same happens If I use local BRAM.
Please help me to know if I miss any configuration.
01-06-2019 07:36 PM
What do you mean you can "see write and read transaction[s]"? Are you using an ILA to observe AXI transfers in the PL?
One thing I learned years ago about Zynq is: don't use PS DMA; use AXI DMA in PL--especially for PL-to-PL transfers.
01-07-2019 02:51 AM
Yes. I am using ILA to observe transactions.
I agreed on your point using AXI DMA but in my case I need to transfer large data between PS-DDR to PL-DDR.
Hope I made clear this time.
Do you have any suggestion on above ?
01-07-2019 05:11 AM
Same suggestion: try using a PL-based AXI DMA instead of PS-based DMA. The former is capable of retrieving data from the PS and PS-DDR, too.
01-16-2019 10:54 PM
01-18-2019 02:11 PM
I think the best place to start is to verify that you set up the destination address correctly. Are you using the ZDMA in scatter gather or simple mode? If you are using simple mode, can you dump the registers for the channel you are using? What is the destination address set to?
If you are using scatter gather mode, can you dump the contents of the first buffer descriptor?
The other thing to look out for is whether the ZDMA is reporting any errors. Check the ZDMA_CH_ISR as it reports a variety of errors.
Please consult UG1087 to identify the address of these registers.