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Registered: ‎09-28-2015

PCIe endpoint initiated transactions

We are using PCIe and a x4 cable to perform board to board comms (using two identical proprietary boards, each with the Zynq XC7Z035).


We use the AXI PCie bridge V2.5 (PG055), one board's FPGA end is built as a PCIe root, the other as a PCIe endpoint. We are using Vivado 2014.4.


I can map a BAR from the endpoint into the root's address space and inintiate mem-read or mem-write transactions from the root which appear in the endpoint's DDR.


What I cannot do is get the Zync ARM on the *endpoint* to initiate a PCIe mem-read or mem-write transaction destined to appear in the root's memory space (root's DDR). I have enabled bus mastering for the endpoint.


Is there a problem with this feature (I saw comments to this effect in another PCIe post) or am I missing some configuration?




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