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Visitor rocco0815
Visitor
702 Views
Registered: ‎11-21-2017

PL writing to DDR --> DDR write access blocked by RTOS?

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Hi there,

 

I think there is an adressing problem but first let me tell what I did:

 

My System: Trenzboard 7020, part "xc7z020clg484-1".

 

I am trying to buffer my ADC Data from FPGA directly to DDR. So i created via HLS a custom IP which is waiting for Temperatur/ADC data and then writes this data  to DDR @baseaddress 0x2000000.

(Code on the bottom of this post )

 

So in Simulation the code works as it should. On my vivado design I placed the pin "ddr" of this custom HLS Ip to constant = "0x2000000". <<< So my baseaddress of this buffer is 0x2000000.

Also I connected this custom IP to my axi_interconnect so there is no need of an extra DMA IP, right?!

 

Now on my SDK, I am running RTOS with the IwIP Echo Server example with following addresses:

 

Bootloader:

 

MEMORY
{
   ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
   ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}

 

 

RT OS with IwIP Echo Server Example:

 

MEMORY
{
   ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0xD664C0
   ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x30000
   ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
}

 

 

So far so good, so my max. used DDR Address for my system is:

0x100000 + = 0xD664C0 = 0xE664C0 <<< Enough away from 0x2000000 (my HLS buffer)

 

So running this setup via SDK debugging or from sd-card the system is working except DDR writing:

On first bootup, no data is written to DDR -> no valid data

 

The point is, after every start of a new debug session via SDK, suddenly there is correct data on DDR @0x2000000

I have a suspicion:

By writing the new data (Bitstream or RTOS) via debugger (JTAG) there is a short time were the CustomIP has write acces to DDR and is writing his data. After the RTOS has booted, the write access has gone and the data are old but were written to DDR.

 

The question is now: Do I have to tell the RTOS something about my address 0x2000000, so that my custom IP has write access to DDR ?

 

Thanks in advance!

 

 

 

HLS CODE:

#########################################################################

 

#include "datalogger.h"

 

unsigned int busTMP121  [ 2];

unsigned int hwCounterTmp121Bk   = 0;
unsigned int dataCounterTmp121   = 0;
unsigned int bufferSizeTmp121    =     120;
                                                
void data_recorder(int *ddr,
                   unsigned int hwCounterTmp121,
                   short         dataTmp121)
{
#pragma HLS INTERFACE m_axi depth=128 port=ddr offset=direct
#pragma HLS INTERFACE ap_ctrl_none port=return

    unsigned int iOffset = 0;

    int i = 0;

 
        // RECORDING
        if(hwCounterTmp121 != hwCounterTmp121Bk)
        {
            hwCounterTmp121Bk = hwCounterTmp121;

            busTmp121[0] = hwCounterTmp121Bk;
            busTmp121[1] = (unsigned int)dataTmp121;

            iOffset = dataCounterTmp121;

            memcpy(ddr+iOffset,busTmp121,2*sizeof(unsigned int));

            dataCounterTmp121 += 2;

            if(dataCounterTmp121 >= bufferSizeTmp121)
            {
                dataCounterTmp121 = 0;
            }
//            dataCounterTmp121 %= (bufferSizeTmp121);
        }
    }
}

 

 

########################################################

 

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Visitor rocco0815
Visitor
777 Views
Registered: ‎11-21-2017

Re: PL writing to DDR --> DDR write access blocked by RTOS?

Jump to solution

What a cool forum... (warning ironic)

Nevertheless, I found finally my problem and the solution:

 

Thanks to hbucher's comment:

 

"Every time you access DDR from the PS, you go through a internal cache. 

Perhaps the data is not being flushed from the PS cache to DDR.

You have to write then flush the cache for that piece of memory with Xil_DCacheFlushRange(addr,size).

This guarantees that the memory is written. 

Before reading, you have to issue Xil_DCacheInvalidateRange(addr,size) to guarantee that your cache is synchronized properly."

 

Source: https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Write-to-DDR-from-PS-read-form-PL-with-custom-IP/m-p/818011/highlight/true#M22415

 

So I had to call  Xil_DCacheInvalidateRange(addr,size)  to get the current data of ddr ram and not the cached ram.

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1 Reply
Visitor rocco0815
Visitor
778 Views
Registered: ‎11-21-2017

Re: PL writing to DDR --> DDR write access blocked by RTOS?

Jump to solution

What a cool forum... (warning ironic)

Nevertheless, I found finally my problem and the solution:

 

Thanks to hbucher's comment:

 

"Every time you access DDR from the PS, you go through a internal cache. 

Perhaps the data is not being flushed from the PS cache to DDR.

You have to write then flush the cache for that piece of memory with Xil_DCacheFlushRange(addr,size).

This guarantees that the memory is written. 

Before reading, you have to issue Xil_DCacheInvalidateRange(addr,size) to guarantee that your cache is synchronized properly."

 

Source: https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Write-to-DDR-from-PS-read-form-PL-with-custom-IP/m-p/818011/highlight/true#M22415

 

So I had to call  Xil_DCacheInvalidateRange(addr,size)  to get the current data of ddr ram and not the cached ram.

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