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Observer migliorin
Registered: ‎03-14-2008

PLB IPIF Master module in the Peripheral

Hello, when i add the IP Peripheral in EDK 9.1, and choose to have a software accessible registers, the wizard generates VHDL code for creating those registers, and also generates example software which accesses those registers.

But when i choose master module, it also generates VHDL code for master module implementation. and also, in the VHDL comments it says how to access and use master module using software, but it doesnt generate any software... for example...here is a piece of comment code:

-- Example code to demonstrate user logic master model functionality
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the IPIF IP master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the IPIF
-- IP master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Bsy (User Logic Master is Busy)
-- bit 2-7 - Spare (Spare Status Bits)
-- IP2IP Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - IP2IP Address (This 32-bit value is used to populate the
-- IP2IP_Addr(0:31) address bus during a Read or Write user
-- logic master operation)
-- IP2Bus Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-31 - IP2Bus Address (This 32-bit value is used to populate the
-- IP2Bus_Addr(0:31) address bus during a Read or Write user
-- logic master operation)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-15 - Transfer Length (This 16-bit value is used to specify the
-- number of bytes (1 to 65,536) to transfer during user logic
-- master read or write operations)
-- BE Register (C_BASEADDR + OFFSET + 0xE):
-- bit 0-7 - IP2Bus master BE (This 8-bit value is used to populate the
-- IP2Bus_MstBE byte enable bus during user logic master read or
-- write operations, only used in single data beat operation)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (A write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the source data address (local) to the ip2ip register
-- 3. write the destination address (remote) to the ip2bus register
-- - note: this address will be put on the target bus address line
-- 4. write 0x0004 to the length register
-- 5. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 6. write 0x0a to the go register, this will start the write operation

i do write some values to those registers, but nothing changes...and nothing happens... maybe i do it in a wrong way.

have anyone worked with this stuff? or maybe know some resources regarding this? i couldnt find anything... i just need to successfully write software in C, to be able to work with the code generated by wizard, so that later, i can remake that code and make it do what i want, and write my own software...thanks
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Observer migliorin
Registered: ‎03-14-2008

Re: PLB IPIF Master module in the Peripheral

ok i tried working with this problem more..let me explain u better. I have 512MB DDR SDRAM memory inmy EDK system, the memory starts from address 0x00000000, and the first byte cell has some data...

i tried to copy this first byte of data, and put it in my software accessable register using PLB Master module.... but it only writes value of 0 (zero) to the slave register....why?

one more thing...later i decided to do this:

Xuint8 byte;
byte = XIo_In8(0x00000000);
xil_printf("byte = : %d\r\n", byte);

and it also copied value of ZERO 0, to the byte variable!!! what is the problem???? maybe this problem deals with the probloem of writing zeros in the slave register using Master module? any ideas?
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