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Observer migliorin
Observer
5,658 Views
Registered: ‎03-14-2008

PLB IPIF Master module is not operating correctly

Hello,

I have generated the PLB Master module peripheral, with the peripheral wizard. Now i want to transfer data from the DDR memory connected to the system to the slave register of the Master module.

Here is how the VHDL code generated by peripheral wizard says to do it:

===================
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the source data address (local) to the ip2ip register
-- 3. write the destination address (remote) to the ip2bus register
-- - note: this address will be put on the target bus address line
-- 4. write 0x0004 to the length register
-- 5. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 6. write 0x0a to the go register, this will start the write operation
=====================

here is a piece of my code:

=====================================================================================
Xuint32 data; // variable for test

// PREPARATION!
// Set the base address of the DDR to a visible value. We will manipulate it later.
XIo_Out32(0xd0000000, 0xABCD1234);

// Write another distinctive value into the first reg (slv_reg0) of the peripheral.
XIo_Out32(XPAR_VIDEO_CTRL_0_BASEADDR + 0x00, 0xAABBCCDD);

data = XIo_In32(0xd0000000);
xil_printf("Value of the DDR (before master transfer) = : %x\r\n", data);

data = XIo_In32(XPAR_VIDEO_CTRL_0_BASEADDR + 0x00);
xil_printf("Value of the slv_reg0 (before master transfer) = : %x\r\n", data);

// COMMANDING THE MASTER!
// Write 0x40 to the control register on the master peripheral
XIo_Out8(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x00, 0x40);

// Write the source address for the write to the IP2IP register on the master peripheral
// In our example, we'll use slv_reg0 in the peripheral.
XIo_Out32(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x04, XPAR_VIDEO_CTRL_0_BASEADDR + 0x00);

// Write the destination address for the write to the IP2BUS register on the master peripheral
// In our example, we'll overwite the same BRAM location that we set earlier.
XIo_Out32(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x08, 0xd0000000);

// Write the length of the transfer (in bytes) to the LENGTH register on the master peripheral
// In our example, we only want to send one word (4 bytes).
XIo_Out16(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x0C, 0x04);

// Write a value for the byte enables to the BE register on the master peripheral
// In our example, we are writing to a 0x???????0 address, so we'll use half of the 64 bit PLB
XIo_Out8(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x0E, 0xf0);

// Write the special "GO" command into the GO Register on the master peripheral
// The GO command is always 0x0A
XIo_Out8(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x0F, 0x0A);

// Wait to see what happens! The DDR address containing 0xABCD1234 should be overwritten with 0xAABBCCDD

data = XIo_In32(0xd0000000);
xil_printf("Value of the DDR (AFTER master transfer) = : %x\r\n", data);
===================================================================================


i used the UART port to print the values, here is what i get when the above code is executed:

===============
Value of the DDR (before master transfer) = : ABCD1234
Value of the slv_reg0 (before master transfer) = : AABBCCDD
Value of the DDR (AFTER master transfer) = : 0
===============


As you see from the code, i am writing the value of 0xABCD1234 to the DDR memory with address - 0xd0000000 (take a look at the address space range picture snapshot attached to this webcase) and this value is successfully written and later being read from the DDR memory before the master operation.

I also write the value of 0xAABBCCDD to the slv_reg0 register. And see that slv_reg0 really contains this value.

Next, i am commanding the master to start the master operation! I am reading 4 bytes from slv_reg0, and sending them to DDR with the address 0xd0000000!

Now! i am trying to read the DDR address 0xd0000000, and i see that it contains the value of 0 (ZERO)!

i dont understand why does the master write value of 0 to the DDR?? maybe the problem is very trivial? where could be my mistake? or the master module doesnt work good with DDR memory? (but it should..)

p.s. same happens when i try to read the DDR memory and write its contents to the slv_reg0 register... slv_reg0 register has the value of 0 (zero) after the master operation...

any ideas? anyone have done it successfully?
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2 Replies
Observer migliorin
Observer
5,641 Views
Registered: ‎03-14-2008

Re: PLB IPIF Master module is not operating correctly

Well i tried the same operation with BRAM! and same thing happens! BRAM is being written with zeroes by Master module!! WHY!! is it some kind of bug or what?? maybe i am doing something wrong, i'd appreciate very much if at least anyone who had such experience will give me a hint!
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Observer migliorin
Observer
5,631 Views
Registered: ‎03-14-2008

Re: PLB IPIF Master module is not operating correctly

Well!!!! it really can make one crazy!

i cannot find answer to this question on any website or forum or google group!

I even opened the webcase, one of the Xilinx engineers showed me example code...but to say true, nothing new, i had the same code...he at least let me know that i was doing everything correct, but his code DID NOT WORK!! it just wrote the value of 0 to he DDR or BRAM... is it a bug or i am missing something????

is there at least anyone who had some experience with master write operation??? please respond!
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