09-22-2016 03:13 AM - edited 09-22-2016 03:15 AM
I'm accessing the PS DDR through HP ports in linux. I'm mapping the DDR address size using 'mmap' and its working without any problem. The below code used for mapping the PS DDR in linux,
off_t dev_base1 = 0x20000000; //( PS DDR Address range 0x0000 0000 to 0x3FFF FFFF)
mapped_base1 = mmap(0, MAP_SIZE1, PROT_READ | PROT_WRITE, MAP_SHARED, memfd1, dev_base1 & ~MAP_MASK1);
if (mapped_base1 == (void *) -1)
printf("Can't map the memory1 to user space.\n");
printf("DDR mapped at address %p.\n", mapped_base1);
mapped_dev_base1 = mapped_base1 + (dev_base1 & MAP_MASK1);
Now in the same C- code I need to add the logic to map the PL DDR. I'm planing to do this as shown below to achieve this.
off_t dev_base_PL = 0x80000000; //( PL DDR Address range 0x8000 0000 to 0xBFFF FFFF)
Then remaining steps will be the same as shown above for PS DDR. Will it work properly??
Now I have axi engine in PL and it has to fetch and write into PL DDR. I'm going to configure the start address to the axi dma engine as "0x80000006". So this is the PL DDR address and will it access the PL DDR ?
Please clear my doubts. Whether I'm trying to do correctly or not?
09-22-2016 03:22 AM
09-22-2016 03:15 PM
09-27-2016 08:50 AM
The dev_base_PL is not the register space address. It's just the starting address of whole DDR address range so that we can access the DDR in linux i.e data write from SD card to DDR using logic in the linux C-code (file operation).
I have 5 AXI master interfaces (4-write masters and 1-read master) in the PL. Previously these all AXI masters connected to the HP ports to access the PS DDR, and it was working very well.
Now, I changed the connection of these AXI masters to the MIG core in the PL to access DDR3 SODIMM memory (PL). For, this I have one interconnect (5s:1m) and this interconnect mater connected to the slave interface of MIG. Please see the image below contains the Address Editor from vivado.
I need to configure the starting address to all the AXI master to write/read from PL DDR. I have configured the address which are with in the range of 0x8000_0000 to 0xBFFF_FFFF. I did not do any change in the existing C-code which is running in the linux apart from the reg configs of address registers of these DMA engines.
These 4 AXI write masters are writing into the PL DDR but read is happening when these writes are done not concurrently i.e
Decoder output are writing but display VDMA fetches the final frame which has done by decoder. decoder decoded around 2500 frames but VDMA fetches and displays 2500th frame only. so I'm suspecting read and write is not happening properly.