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Voyager
Voyager
2,235 Views
Registered: ‎05-31-2012

Problem with dual microblaze

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I read a lot of documentation on dual microblaze design, but i have problem to start the second microblaze from the external memory. It remains on address 0x8 , when i download the elf file it starts running and can't stop.

If i run the second microblaze from the bram memory i have no problem, i can read and write the external memory with xmd commands mrd and mwr.

 

I modified the linker script of the 2 programs to allow the 2 processors to not overwrite the shared external memory...

In the launch option i set "reset only the processor" as i read it somewhere..

I haven't connected the IP port of both microblaze...

Thank you for any suggestion

 

This is the .mhs

 

PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RS232_Uart_2_sout = RS232_Uart_2_sout, DIR = O
 PORT RS232_Uart_2_sin = RS232_Uart_2_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 100000000
 PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 100000000
 PORT DDR3_FPGA_MEM1_A = DDR3_FPGA_MEM1_A, DIR = O, VEC = [12:0]
 PORT DDR3_FPGA_MEM1_BA = DDR3_FPGA_MEM1_BA, DIR = O, VEC = [2:0]
 PORT DDR3_FPGA_MEM1_CAS_N = DDR3_FPGA_MEM1_CAS_N, DIR = O
 PORT DDR3_FPGA_MEM1_CK = DDR3_FPGA_MEM1_CK, DIR = O, SIGIS = CLK
 PORT DDR3_FPGA_MEM1_CK_N = DDR3_FPGA_MEM1_CK_N, DIR = O, SIGIS = CLK
 PORT DDR3_FPGA_MEM1_CKE = DDR3_FPGA_MEM1_CKE, DIR = O
 PORT DDR3_FPGA_MEM1_DQM = DDR3_FPGA_MEM1_DQM, DIR = O, VEC = [1:0]
 PORT DDR3_FPGA_MEM1_ODT = DDR3_FPGA_MEM1_ODT, DIR = O
 PORT DDR3_FPGA_MEM1_RAS_N = DDR3_FPGA_MEM1_RAS_N, DIR = O
 PORT DDR3_FPGA_MEM1_RESET_N = DDR3_FPGA_MEM1_RESET_N, DIR = O
 PORT DDR3_FPGA_MEM1_PARITY = DDR3_FPGA_MEM1_PARITY, DIR = O
 PORT DDR3_FPGA_MEM1_WE_N = DDR3_FPGA_MEM1_WE_N, DIR = O
 PORT DDR3_FPGA_MEM1_DQ = DDR3_FPGA_MEM1_DQ, DIR = IO, VEC = [15:0]
 PORT DDR3_FPGA_MEM1_DQS = DDR3_FPGA_MEM1_DQS, DIR = IO, VEC = [1:0]
 PORT DDR3_FPGA_MEM1_DQS_N = DDR3_FPGA_MEM1_DQS_N, DIR = IO, VEC = [1:0]


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_100_0000MHz
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN axi_intc
 PARAMETER INSTANCE = microblaze_0_intc
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE INTERRUPT = microblaze_0_interrupt
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT Intr = debug_module_Interrupt & RS232_Interrupt
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.10.c
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.10.c
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.40.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0x80000000
 PARAMETER C_ICACHE_HIGHADDR = 0x87ffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0x80000000
 PARAMETER C_DCACHE_HIGHADDR = 0x87ffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 BUS_INTERFACE INTERRUPT = microblaze_0_interrupt
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHz
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_MB_DBG_PORTS = 2
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 BUS_INTERFACE MBDEBUG_1 = debug_module_MBDEBUG_1
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT Interrupt = debug_module_Interrupt
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_GROUP = PLLE0
 PARAMETER C_CLKOUT1_FREQ = 400000000
 PARAMETER C_CLKOUT1_PHASE = 337.5
 PARAMETER C_CLKOUT1_GROUP = PLLE0
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_GROUP = PLLE0
 PARAMETER C_CLKOUT2_BUF = FALSE
 PARAMETER C_CLKOUT3_FREQ = 25000000
 PARAMETER C_CLKOUT3_PHASE = 9.84375
 PARAMETER C_CLKOUT3_DUTY_CYCLE = 0.0625
 PARAMETER C_CLKOUT3_GROUP = PLLE0
 PARAMETER C_CLKOUT3_BUF = FALSE
 PARAMETER C_CLKOUT4_FREQ = 200000000
 PARAMETER C_CLKOUT4_GROUP = PLLE0
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT0 = clk_100_0000MHz
 PORT RST = RESET
 PORT CLKIN = CLK
 PORT CLKOUT1 = clock_generator_0_CLKOUT1
 PORT CLKOUT2 = clock_generator_0_CLKOUT2
 PORT CLKOUT3 = clock_generator_0_CLKOUT3
 PORT CLKOUT4 = clock_generator_0_CLKOUT4
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_100_0000MHz
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_DATA_WIDTH = 128
 PORT interconnect_aclk = clk_100_0000MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
 PORT Interrupt = RS232_Interrupt
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_uart2
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x50600000
 PARAMETER C_HIGHADDR = 0x5060ffff
 BUS_INTERFACE S_AXI = microblaze_1_axi_periph
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT TX = RS232_Uart_2_sout
 PORT RX = RS232_Uart_2_sin
 PORT Interrupt = RS232_Interrupt_uart2
END

BEGIN axi_7series_ddrx
 PARAMETER INSTANCE = axi_7series_ddrx_0
 PARAMETER HW_VER = 1.07.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_IC & microblaze_0.M_AXI_DC & microblaze_1.M_AXI_IC & microblaze_1.M_AXI_DC
 PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E
 PARAMETER C_DM_WIDTH = 2
 PARAMETER C_DQ_WIDTH = 16
 PARAMETER C_DQS_WIDTH = 2
 PARAMETER C_RTT_NOM = 60
 PARAMETER C_USE_CS_PORT = 0
 PARAMETER C_PLLE2_EXT_LOC = X1Y1
 PARAMETER C_CLKOUT0_PHASE = 337.5
 PARAMETER C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE = 4
 PARAMETER C_INTERCONNECT_S_AXI_READ_ACCEPTANCE = 4
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_S_AXI_BASEADDR = 0x80000000
 PARAMETER C_S_AXI_HIGHADDR = 0x87ffffff
 BUS_INTERFACE S_AXI = axi4_0
 PORT freq_refclk = clock_generator_0_CLKOUT1
 PORT mem_refclk = clock_generator_0_CLKOUT2
 PORT sync_pulse = clock_generator_0_CLKOUT3
 PORT clk_ref = clock_generator_0_CLKOUT4
 PORT clk = clk_100_0000MHz
 PORT ddr_addr = DDR3_FPGA_MEM1_A
 PORT ddr_ba = DDR3_FPGA_MEM1_BA
 PORT ddr_cas_n = DDR3_FPGA_MEM1_CAS_N
 PORT ddr_ck_p = DDR3_FPGA_MEM1_CK
 PORT ddr_ck_n = DDR3_FPGA_MEM1_CK_N
 PORT ddr_cke = DDR3_FPGA_MEM1_CKE
 PORT ddr_dm = DDR3_FPGA_MEM1_DQM
 PORT ddr_odt = DDR3_FPGA_MEM1_ODT
 PORT ddr_ras_n = DDR3_FPGA_MEM1_RAS_N
 PORT ddr_reset_n = DDR3_FPGA_MEM1_RESET_N
 PORT ddr_parity = DDR3_FPGA_MEM1_PARITY
 PORT ddr_we_n = DDR3_FPGA_MEM1_WE_N
 PORT ddr_dq = DDR3_FPGA_MEM1_DQ
 PORT ddr_dqs_p = DDR3_FPGA_MEM1_DQS
 PORT ddr_dqs_n = DDR3_FPGA_MEM1_DQS_N
 PORT pll_lock = proc_sys_reset_0_Dcm_locked
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER HW_VER = 8.40.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_STREAM_INTERCONNECT = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_ICACHE_LINE_LEN = 8
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_ICACHE_BASEADDR = 0x80000000
 PARAMETER C_ICACHE_HIGHADDR = 0x87ffffff
 PARAMETER C_DCACHE_BASEADDR = 0x80000000
 PARAMETER C_DCACHE_HIGHADDR = 0x87ffffff
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 BUS_INTERFACE M_AXI_DP = microblaze_1_axi_periph
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = debug_module_MBDEBUG_1
 BUS_INTERFACE DLMB = microblaze_1_dlmb
 BUS_INTERFACE ILMB = microblaze_1_ilmb
 PORT CLK = clk_100_0000MHz
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = microblaze_1_axi_periph
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = clk_100_0000MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_1_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_1_d_bram_cntlr
 PARAMETER HW_VER = 3.10.c
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = microblaze_1_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_cntlr_BRAM_PORT
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_1_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTB = microblaze_1_d_bram_cntlr_BRAM_PORT
 BUS_INTERFACE PORTA = microblaze_1_i_bram_cntlr_BRAM_PORT
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_1_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_1_i_bram_cntlr
 PARAMETER HW_VER = 3.10.c
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = microblaze_1_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_cntlr_BRAM_PORT
END

 

dual_mb.png
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1 Solution

Accepted Solutions
Voyager
Voyager
2,797 Views
Registered: ‎05-31-2012

Re: Problem with dual microblaze

Jump to solution

I think i have resolved, in the second Microblaze i had to turn on  "Use cache links for all memory accesses" for data and instruction caches...

 

don't know what this option does, someone can explain it?

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1 Reply
Voyager
Voyager
2,798 Views
Registered: ‎05-31-2012

Re: Problem with dual microblaze

Jump to solution

I think i have resolved, in the second Microblaze i had to turn on  "Use cache links for all memory accesses" for data and instruction caches...

 

don't know what this option does, someone can explain it?

0 Kudos