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Problems with FSL Bus in Microblaze

Observer
Posts: 26
Registered: ‎09-24-2011

Problems with FSL Bus in Microblaze

Hello, I have SPARTAN 6 SP 605 board and ISE 13.2. I created a project of the embedded system based on Microblaze with my core on FSL bus. But in the process of generation of the programming file occur the following error:

ERROR:MapLib:978 - LUT6 symbol
"system_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Using_Streaming.Using_FSL.FSL_Module_I/Mmux_EX_FSL_Control_Error11" (output
signal=system_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/EX_FSL_Control_Er
ror) has an equation that uses input pin I4, which no longer has a connected
signal. Please ensure that all the pins used in the equation for this LUT
have signals that are not trimmed (see Section 5 of the Map Report File for
details on which signals were trimmed).

I don't know where is FSL_Control_Error, I think I don't have direct access to this signal.

My MHS:
PARAMETER VERSION = 2.1.0


PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
PORT External_INT_req = External_INT_req_0, DIR = I, SIGIS = INTERRUPT
PORT axi_gpio_0_GPIO_IO_O_pin = axi_gpio_0_GPIO_IO_O, DIR = O, VEC = [3:0]
PORT fsl_interface_0_FSL_Clk_100MHz_pin = fsl_interface_0_FSL_Clk_100MHz, DIR = O
PORT fsl_interface_0_Mb_ip_reset_pin = fsl_interface_0_Mb_ip_reset, DIR = O
PORT fsl_interface_0_Add_wr_ready_pin = fsl_interface_0_Add_wr_ready, DIR = O
PORT fsl_interface_0_Ad_data_rd_ready_pin = fsl_interface_0_Ad_data_rd_ready, DIR = O
PORT fsl_interface_0_Ad_data_wr_ready_pin = fsl_interface_0_Ad_data_wr_ready, DIR = O
PORT fsl_interface_0_Data_rdBus_pin = fsl_interface_0_Data_rdBus, DIR = I, VEC = [0:31]
PORT fsl_interface_0_Addread_pin = fsl_interface_0_Addread, DIR = O, VEC = [31:0]
PORT fsl_interface_0_Addwrite_pin = fsl_interface_0_Addwrite, DIR = O, VEC = [31:0]
PORT fsl_interface_0_FIFO_rd_Full_pin = fsl_interface_0_FIFO_rd_Full, DIR = O
PORT fsl_interface_0_Add_rd_ready_pin = fsl_interface_0_Add_rd_ready, DIR = O
PORT fsl_interface_0_Data_wrBus_pin = fsl_interface_0_Data_wrBus, DIR = O, VEC = [0:31]


BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
PORT MB_Reset = proc_sys_reset_0_MB_Reset
PORT Slowest_sync_clk = clk_100_0000MHz
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
PORT Ext_Reset_In = RESET
PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_ilmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = microblaze_0_ilmb
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_dlmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
PARAMETER INSTANCE = microblaze_0_bram_block
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 8.20.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0xba408000
PARAMETER C_ICACHE_HIGHADDR = 0xba40bfff
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_BASEADDR = 0xba408000
PARAMETER C_DCACHE_HIGHADDR = 0xba40bfff
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 8192
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER C_FSL_LINKS = 1
PARAMETER C_USE_EXTENDED_FSL_INSTR = 0
BUS_INTERFACE M_AXI_DP = axi4lite_0
BUS_INTERFACE M_AXI_DC = axi4_0
BUS_INTERFACE M_AXI_IC = axi4_0
BUS_INTERFACE DEBUG = microblaze_0_debug
BUS_INTERFACE SFSL0 = fsl_v20_1
BUS_INTERFACE DLMB = microblaze_0_dlmb
BUS_INTERFACE ILMB = microblaze_0_ilmb
BUS_INTERFACE MFSL0 = fsl_v20_0
PORT MB_RESET = proc_sys_reset_0_MB_Reset
PORT CLK = clk_100_0000MHz
PORT INTERRUPT = axi_intc_0_Irq
END

BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.b
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_UART = 1
PARAMETER C_BASEADDR = 0x74800000
PARAMETER C_HIGHADDR = 0x7480ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT S_AXI_ACLK = clk_100_0000MHz
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.02.a
PARAMETER C_CLKIN_FREQ = 200000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT1_FREQ = 200000000
PARAMETER C_CLKOUT1_PHASE = 0
PORT LOCKED = proc_sys_reset_0_Dcm_locked
PORT CLKOUT0 = clk_100_0000MHz
PORT RST = RESET
PORT CLKIN = CLK
PORT CLKOUT1 = clk_200_0000MHz
END

BEGIN bram_block
PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
BUS_INTERFACE PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
END

BEGIN axi_bram_ctrl
PARAMETER INSTANCE = axi_bram_ctrl_0
PARAMETER HW_VER = 1.02.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
PARAMETER C_S_AXI_BASEADDR = 0xba408000
PARAMETER C_S_AXI_HIGHADDR = 0xba40bfff
BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
BUS_INTERFACE S_AXI = axi4_0
PORT S_AXI_ACLK = clk_100_0000MHz
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi4lite_0
PARAMETER HW_VER = 1.03.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
PORT INTERCONNECT_ACLK = clk_100_0000MHz
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi4_0
PARAMETER HW_VER = 1.03.a
PORT interconnect_aclk = clk_100_0000MHz
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_gpio
PARAMETER INSTANCE = axi_gpio_0
PARAMETER HW_VER = 1.01.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
PARAMETER C_INTERRUPT_PRESENT = 0
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT GPIO_IO_O = axi_gpio_0_GPIO_IO_O
END

BEGIN axi_intc
PARAMETER INSTANCE = axi_intc_0
PARAMETER HW_VER = 1.01.a
PARAMETER C_IRQ_IS_LEVEL = 0
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT Irq = axi_intc_0_Irq
PORT Intr = External_INT_req_0
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_0
PARAMETER HW_VER = 2.11.e
PARAMETER C_FSL_DEPTH = 16
PARAMETER C_IMPL_STYLE = 0
PORT FSL_Clk = clk_100_0000MHz
PORT SYS_Rst = RESET
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_1
PARAMETER HW_VER = 2.11.e
PARAMETER C_FSL_DEPTH = 64
PARAMETER C_IMPL_STYLE = 0
PORT FSL_Clk = clk_100_0000MHz
PORT SYS_Rst = RESET
END

BEGIN fsl_interface
PARAMETER INSTANCE = fsl_interface_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE SFSL = fsl_v20_0
BUS_INTERFACE MFSL = fsl_v20_1
PORT ext_clk_200MHz = clk_200_0000MHz
PORT FSL_Clk_100MHz = fsl_interface_0_FSL_Clk_100MHz
PORT INT_user = External_INT_req_0
PORT Mb_ip_reset = fsl_interface_0_Mb_ip_reset
PORT Add_wr_ready = fsl_interface_0_Add_wr_ready
PORT Ad_data_rd_ready = fsl_interface_0_Ad_data_rd_ready
PORT Ad_data_wr_ready = fsl_interface_0_Ad_data_wr_ready
PORT Data_rdBus = fsl_interface_0_Data_rdBus
PORT Addread = fsl_interface_0_Addread
PORT Addwrite = fsl_interface_0_Addwrite
PORT FIFO_rd_Full = fsl_interface_0_FIFO_rd_Full
PORT Add_rd_ready = fsl_interface_0_Add_rd_ready
PORT Data_wrBus = fsl_interface_0_Data_wrBus
END

regard...