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Observer karthikeasan
Observer
180 Views
Registered: ‎03-26-2013

Procedure to loop back PL clock

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Hi,

I have enabled pl_clk2 to send it to SEMIP in PL.

Is anyone knows the procedure to loop back pl_clk2 to PS  in block design ?

 

Thanks

KS 

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1 Solution

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Voyager
Voyager
70 Views
Registered: ‎02-01-2013

Re: Procedure to loop back PL clock

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Ok. I get it now...

pl_clk0 is not being "looped back" to the PSU in this design; it's simply being fanned out to become the source clock for several things. 

I'm not entirely sure why the clock is connected to maxihpm0_lpd_aclk port of the PSU. That port is used to provide the clock to the PSU that would be used to clock data into and out of the M_AXI_HPM0_LPD interface--but that interface is (apparently) unused in the design. It's possible that that connection is shown to remind you that if you do use the interface, you must connect the raw clock output from the PSU to the maxihpm0_lpd_aclk port of the PSU, instead of connecting the gated version that's used for the demonstrated circuitry. That clock connection really has no bearing on the rest of the demonstrated circuitry.

I 'skimmed' the video. This is not an entry-level tutorial. A lot of significant and involved steps were mentioned ony in passing. I hope this isn't your first FPGA tutorial.

-Joe G.

P.S. Input-clock ports on the PSU are enabled automatically when you enable the associated AXI interface. The interfaces themselves are enabled through the PSU Re-customize IP Wizard:

2019-02-11_21-57-25.jpg

 

4 Replies
Voyager
Voyager
140 Views
Registered: ‎02-01-2013

Re: Procedure to loop back PL clock

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Loop it back for what? 

If you're connecting the SEMI IP to the PS using an AXI port on the PS, when you enabled that port, the clock input associated with that port should have emerged on the left side of the PS block. Assuming you're using pl_clk2 as the AXI clock input for the SEMI IP, you would also connect pl_clk2 to the clock input on the PS block.

2019-02-07_18-56-44.jpg

That clock would also be used to clock the AXI Interconnect between the PS block and the SEMI IP, as well as the Processor System Reset IP you'll need to finish-off the design.

-Joe G.

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Observer karthikeasan
Observer
82 Views
Registered: ‎03-26-2013

Re: Procedure to loop back PL clock

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Thanks you for your quick reply.

I am trying to implement the example design shown in the link below. It is 4 wire communication(clk, clk_enable, uart_tx, & uart_rx).

https://www.xilinx.com/video/fpga/seu-solution-through-four-signals.html

PS is communicating with SEMIP in PL via UART1(EMIOs). The pl_clk2 is the clock source going from PS to SEMIP in PL.

If you see in the example design, pl_clk0 is looped back to maxihpm0_lpd_aclk. This is what i am not clear.

Can you please tell me how did you enable ''maxihpm0_fpd_aclk' in PS ?

Thanks

KS

Example_design.PNG
Example_Block_design.PNG
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Voyager
Voyager
71 Views
Registered: ‎02-01-2013

Re: Procedure to loop back PL clock

Jump to solution

 

Ok. I get it now...

pl_clk0 is not being "looped back" to the PSU in this design; it's simply being fanned out to become the source clock for several things. 

I'm not entirely sure why the clock is connected to maxihpm0_lpd_aclk port of the PSU. That port is used to provide the clock to the PSU that would be used to clock data into and out of the M_AXI_HPM0_LPD interface--but that interface is (apparently) unused in the design. It's possible that that connection is shown to remind you that if you do use the interface, you must connect the raw clock output from the PSU to the maxihpm0_lpd_aclk port of the PSU, instead of connecting the gated version that's used for the demonstrated circuitry. That clock connection really has no bearing on the rest of the demonstrated circuitry.

I 'skimmed' the video. This is not an entry-level tutorial. A lot of significant and involved steps were mentioned ony in passing. I hope this isn't your first FPGA tutorial.

-Joe G.

P.S. Input-clock ports on the PSU are enabled automatically when you enable the associated AXI interface. The interfaces themselves are enabled through the PSU Re-customize IP Wizard:

2019-02-11_21-57-25.jpg

 

Observer karthikeasan
Observer
44 Views
Registered: ‎03-26-2013

Re: Procedure to loop back PL clock

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Joe,

Thank you very much.

I could loop back to maxihpm0_lpd_aclk . Thank you for your detailed information.

I have worked many FPGA projects but this is my first Zynq Ultrascale+ MPSoC project.

I am just following the example design and it was not clear in demo video that why clock was looped back to PS.

I will try to explore further.

Thanks

KS

 

 

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