We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer olagrottvik
Registered: ‎12-04-2017

Provoke AXI DMA IOC interrupt from PL without delimiter word

I have a setup an AXI DMA with direct register mode S2MM and using a cyclic assertion of the TLAST signal to provoke the DMA to interrupt. However, my PL logic does not know when the final data word is being processed, and thus some data can be stuck in the DMA without an assertion of the interrupt to the processor. Is there a way to provoke the DMA to assert the interrupt?


Right now my workaround is to have a register that provokes a flush of the DMA by writing a delimiter word to the AXI-Stream FIFO with TLAST asserted. However, I would like to not have to do this and get this annoying delimiter word in the output stream. I have tried to write a delimiter word with TLAST asserted and TKEEP = all zeroes. However, this does not provoke the DMA into an interrupt.


Also, turning off or resetting the DMA does not seem to make it flush the last transfer (i.e. IOC_IRQ).


Does this need to be handled by the software somehow or can it be done from the PL?


PS: Is this solvable by enabling scatter-gather and having a timeout of the DMA? Since I have only one channel in one direction it was my impression that scatter-gather is overkill.

0 Kudos