01-07-2019 09:41 PM - edited 01-11-2019 02:19 AM
EDIT: I am able to read and write to registers hanging on the mmi64_axi bus when I use the same clock as the processor is running on (100MHz). When everything else is same except I use a generated clock of 8Mhz, and a push button Reset, the system doesn't work. I can provide more information if needed. Any idea where I might be going wrong with this one?
I have the following setup in Vivado IPI:
I want to read and write to the registers of the AXI port I've made external through baremetal apps first and then through linux. I know the address map of it through Address Editor. How should I go about with it? I tried looking for xilinx header files for functions to read and write. I am not able to find it. Any help is appreciated
More info: clk_out1 is 8 MHz. I tried accessing the registers through __raw_readl in linux kernel module, but the board's linux system just hangs and I've to reboot the board again.
I can provide more information
01-10-2019 03:52 AM
From the linux userspace, you can use devmem to access the physical memory of your device.
Hope that helps,
01-10-2019 07:51 AM
I dont think there is a register space for the AXI clock Converter. The config is done in the HW in the IPI design
01-10-2019 08:19 AM
For bare-metal software, you can use the IO functions defined in xil_io.h.
01-11-2019 02:21 AM
01-11-2019 02:38 AM
Are you sure your other clock is up? And the polarity of the reset signal is correct?
01-11-2019 02:50 AM
01-11-2019 03:15 AM
01-11-2019 04:06 AM
I have tried a similar simple example, but with the processor clock as the clock feeding my peripheral. Now, however, I am trying to use a smaller 8 MHz clock and push-button reset. I am not sure where I am going wrong. Any suggestions or clues?
I will also look into the link you sent meanwhile.
01-11-2019 04:51 AM
Are you following these AXI-Lite clock requirements from UG902?
• AXI4-Lite interface clock must be synchronous to the clock used for the synthesized logic (ap_clk). That is, both clocks must be derived from the same master generator clock.
• AXI4-Lite interface clock frequency must be equal to or less than the frequency of the clock used for the synthesized logic (ap_clk).
I've had issues with the AXI-Lite interfaces on HLS cores when I didn't follow those requirements.
01-15-2019 02:38 AM