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Adventurer
Adventurer
6,274 Views
Registered: ‎02-05-2013

Relative placement error on fpga

Hi,

    Im creating a design with 7 series fpga xc7k160t-1ffg676 using microblaze and with ethernet interface on it . During map process, the following error occurs :

 

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs] for the component
   emb_eth_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMII.I_GMII/gmii
   _interface/GEN_V6.GEN_IO.bufio_gmii_rx_clk of type BUFIO for the following
   reason.
   The reason for this issue:
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.  A problem was found where we should
   place BUFIO
   emb_eth_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMII.I_GMII/gmii
   _interface/GEN_V6.GEN_IO.bufio_gmii_rx_clk off the edge of the chip in order
   to satisfy the relative placement requirement of this logic. The following
   components are part of this structure:

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Even PlanAhead doesnt allow to assign the specific fpga loc to the axi_ethernet_0_gmii_rx_clk pin with error telling the relative placement requirements cannot be met .

Any ideas to resolve this ??

 

-San

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9 Replies
Xilinx Employee
Xilinx Employee
6,264 Views
Registered: ‎09-20-2012

Re: Relative placement error on fpga

Hi,

If bufio is directly being driven by top level port, then the port has to be locked to a clock capable pin.
Try locking the bufio input port to a clock capable pin (MRCC or SRCC).

Thanks,
Deepika.
Thanks,
Deepika.
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Adventurer
Adventurer
6,229 Views
Registered: ‎02-05-2013

Re: Relative placement error on fpga

Hi Deepika ,

                 I hv given bufio for the GMII_RX_CLK_pin and assigned to SRCC pin as well as tried with MRCC pin also. Getting the same error but with additional line telling TIEOFF_X0Y76 site is locked.Any other work arounds for this issue ?? Kindly help

 

-San

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Xilinx Employee
Xilinx Employee
6,226 Views
Registered: ‎09-20-2012

Re: Relative placement error on fpga

Hi San,

 

Can you post the complete error message and the schematic of the BUFIO mentioned in the error?

 

Did you lock the IO port to P-type SRCC or MRCC? If you have locked them to site of n-type then try to locking them to p_type site. 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
6,219 Views
Registered: ‎02-05-2013

Re: Relative placement error on fpga

Initially it was connected to n type mrcc pin now I have connected the RX_CLK_pin to p type MRCC  and got the follwing error :

 

ERROR:Place:906 - Components driven by IO clock net
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> can't be placed and routed
   because location constraints are causing the clock region rules to be
   violated. IO Clock net
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> is being driven by BUFIO
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.GEN_IO.bufio_gmii_rx_clk> locked to site
   "BUFIO_X0Y6" Because of this location contraint,
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> can only drive clock
   region "CLOCKREGION_X0Y1". The following components driven by
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> have been locked to sites
   outside of these clock regions:
   microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMI
   I.I_GMII/gmii_interface/rx_dv_to_mac (Locked Site: ILOGIC_X0Y249
   CLOCKREGION_X0Y4)
   microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMI
   I.I_GMII/gmii_interface/rx_er_to_mac (Locked Site: ILOGIC_X0Y248
   CLOCKREGION_X0Y4)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> to ensure that they follow
   the clock region rules of the architecture. For more information on the clock
   region rules, please refer to the architecture user's guide. To debug your
   design with partially routed design, please allow mapper/placer to finish the
   execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

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Xilinx Employee
Xilinx Employee
6,215 Views
Registered: ‎09-20-2012

Re: Relative placement error on fpga

Hi San,

 

So, the original issue is resolved.

 

The new error is due to limitations of BUFIO. As the error says the BUFIO can drive a single I/O clock network in the same region/bank. In your design you have the BUFIO in clockregion X0Y1 (I guess this clockregion will be same as that of the clockregion of RX_CLK_pin IOB). However the BUFIO is driving loads(located in clockregion X0Y4) which are outside the clockregion X0Y1.

 

If in your design there are large number of IO resources (which span more than one clock region) and you want to supply single clock signal to all these resources you may have to use combination of BUFMR and BUFIO as described in page-102 (Clocking Across multiple regions) of UG472 http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Adventurer
Adventurer
6,188 Views
Registered: ‎02-05-2013

Re: Relative placement error on fpga

Hi Deepika,

                Now, I have tried with BUFMRCE and BUFIO. Getting the following error :

 

ERROR:Place:906 - Components driven by IO clock net
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> can't be placed and routed
   because location constraints are causing the clock region rules to be
   violated. IO Clock net
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> is being driven by BUFIO
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.GEN_IO.bufio_gmii_rx_clk> locked to site
   "BUFIO_X0Y6" Because of this location contraint,
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> can only drive clock
   region "CLOCKREGION_X0Y1". The following components driven by
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> have been locked to sites
   outside of these clock regions:
   microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMI
   I.I_GMII/gmii_interface/rx_dv_to_mac (Locked Site: ILOGIC_X0Y249
   CLOCKREGION_X0Y4)
   microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMI
   I.I_GMII/gmii_interface/rx_er_to_mac (Locked Site: ILOGIC_X0Y248
   CLOCKREGION_X0Y4)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by
   <microblaze_ddr_test1_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GM
   II.I_GMII/gmii_interface/GEN_V6.gmii_rx_clk_bufio> to ensure that they follow
   the clock region rules of the architecture. For more information on the clock
   region rules, please refer to the architecture user's guide. To debug your
   design with partially routed design, please allow mapper/placer to finish the
   execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

There is no primitive structure given for BUFMR , so used BUFMRCE . The doc you mentioned says using BUFMRCE is allowed with BUFIO. What is the issue now ? kindly help

 

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Xilinx Employee
Xilinx Employee
6,185 Views
Registered: ‎09-20-2012

Re: Relative placement error on fpga

Hi,

 

Looks like you are still using single BUFIO to drive all IO resources.

 

BUFMR -- BUFIO

 

You need to make use of more than one BUFIO (up to 3) to drive the loads and these BUFIO have to be driven from BUFMR. Something like below

 

 

BUFMR ----  BUFIO 1

                |--- BUFIO 2

                |--- BUFIO 3

 

 

Later ensure that loads driven by each of the BUFIO is in the same region as that of BUFIO. This can be done by creating area groups as mentioned in "Use Cases" section page-103 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
6,166 Views
Registered: ‎02-05-2013

Re: Relative placement error on fpga

Hi,

      Thanks for the help. I dont think BUFMR is also usable in my case. The signals which the clk pin drives are 3 clock regions away from the MRCC pin location. BUFMR can be used only for adjacent regions. So, Im changing the pin locations in schematic accordingly. I wanted to know if cascading as shown below is allowed for BUFMR to reach distant clock regions

 

BUFMR -- BUFIO -- BUFMR --BUFIO  ??

 

-San

 

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Xilinx Employee
Xilinx Employee
6,160 Views
Registered: ‎09-20-2012

Re: Relative placement error on fpga

Hi San,

 

A BUFIO cannot drive BUFMR. So I dont think the structure which you posted is feasible.

 

You may have to change the IO lock constraints 

 

Thanks,

Deepika.

Thanks,
Deepika.
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