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Adventurer
Adventurer
342 Views
Registered: ‎10-02-2014

Rename PS7 clocks

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Hello,

We are using a zynq based design, where the PS supplies the clock to the PL.

from the system_processing_system7_0_0.xdc read only autogenerated file i have the following clock constraints:

############################################################################
############################################################################
############################################################################
# Clock constraints                                                        #
############################################################################
create_clock -name clk_fpga_3 -period "20" [get_pins "PS7_i/FCLKCLK[3]"]
set_input_jitter clk_fpga_3 0.6
#The clocks are asynchronous, user should constrain them appropriately.#
create_clock -name clk_fpga_0 -period "6.666" [get_pins "PS7_i/FCLKCLK[0]"]
set_input_jitter clk_fpga_0 0.19998
#The clocks are asynchronous, user should constrain them appropriately.#
create_clock -name clk_fpga_2 -period "5.333" [get_pins "PS7_i/FCLKCLK[2]"]
set_input_jitter clk_fpga_2 0.15999
#The clocks are asynchronous, user should constrain them appropriately.#
create_clock -name clk_fpga_1 -period "40" [get_pins "PS7_i/FCLKCLK[1]"]
set_input_jitter clk_fpga_1 1.2
#The clocks are asynchronous, user should constrain them appropriately.#

I don't like those names, but there is no way to rename them, and if I issue

get_pins "PS7_i/FCLKCLK[1]"

after the synthesis i get

WARNING: [Vivado 12-508] No pins matched 'PS7_i/FCLKCLK[1]'.

because I guess the clock is not existing at that stage.

How can i mangle the PS/ clocks in my constraints by using meaningful names?

Thanks,

Marco

 

 

 

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1 Solution

Accepted Solutions
222 Views
Registered: ‎01-22-2015

Re: Rename PS7 clocks

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Marco,

       Why is it so difficult?
I feel your pain.  I was afraid that create_generated_clock would fail because UG903 says: “Only auto-derived clocks can be renamed with this mechanism” – and I couldn’t find that PS7 clocks are considered “auto-derived”.

I will continue to suggest to Xilinx that they somehow give us access to those read-only xdc-files, which would provide an easy solution to what you are trying to do.

Alas, I see no solution – sorry.

Mark

PS. I see the word “alfa” in your post.  I had a 1976 Alfa Romeo Spider Veloce for many years.  I really miss that car.

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9 Replies
294 Views
Registered: ‎01-22-2015

Re: Rename PS7 clocks

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Hi Marco,

   …because I guess the clock is not existing at that stage.
Yes, clock names/constraints are often not recognized until implementation.   If the synthesis warnings about clock names/constraints are not repeated during implementation, then all is well. 

Note: if you open the implemented design and type get_clocks in the Tcl Console then you should see the clock names, (clk_fpga_0, clk_fpga_1, clk_fpga_2, clk_fpga_3).

     I don't like those names, but there is no way to rename them
Those auto-generated, read-only files make life difficult for us.  If the file was not read-only then we could simply change “-name clk_fpga_3” to “-name meaningful_name”.

Try placing the following command at the top of your project xdc-file, which allows you to use $meaningful_name in the rest of the project xdc-file instead of clk_fpga_3.

     set  meaningful_name  clk_fpga_3

Cheers,
Mark

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Adventurer
Adventurer
277 Views
Registered: ‎10-02-2014

Re: Rename PS7 clocks

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It's a very nice suggestion, but, correct me if 'm wrong, I will not have the "meaningful name" in the reports, right?

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268 Views
Registered: ‎01-22-2015

Re: Rename PS7 clocks

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Marco,

     I will not have the "meaningful name" in the reports, right?
You are correct.

Sometimes the configuration wizard for IP allows you to rename clocks. However, my quick look at document, PG082, for the PS7 indicates that there are very few configurable parameters for the clocks because it is a “hard IP”. -ugh

Sometimes you can use create_generated_clock to “officially” change a clock name (ie. the new clock name will appear in the reports). The method is described in UG835 (pg282) and UG903 (pg 91) and is somewhat restrictive - but might work for you.  Try the following to change clk_fpga_3 to meaningful_name:

     create_generated_clock  -name  meaningful_name  [get_pins "PS7_i/FCLKCLK[3]"]


Then..... I'm out of ideas.

Cheers,
Mark

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Adventurer
Adventurer
262 Views
Registered: ‎10-02-2014

Re: Rename PS7 clocks

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create_generated_clock is a "rename" but it will not accept the old name as parameter, but it will require the source object instead.

Is there a way to get the source_object from the clock name?

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Registered: ‎01-22-2015

Re: Rename PS7 clocks

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The following should show all properties for your clock name, clk_fpga_3, including the SOURCE.    
     report_property [get_clocks clk_fpga_3]

 

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Adventurer
Adventurer
234 Views
Registered: ‎10-02-2014

Re: Rename PS7 clocks

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at the end the constraint that i wrote is the following:

create_generated_clock -name REGS_CLK   [get_pins [get_property  SOURCE_PINS [get_clocks clk_fpga_3]]] 

but it looks like Vivado has an excuse for everything...

ERROR: [Constraints 18-851] Could not find an automatically derived clock matching the supplied criteria for renaming.
Resolution: Review the create_generated_clock renaming specification. Use the report_clocks command to obtain the details of currently defined clocks and ensure that the create_generated_clock rename constraint specifies appropriate data to select one generated clock for renaming. Verify that you are attempting to rename a tool derived generated clock, and not a user defined generated clock.
report_clocks
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Thu Jan 10 14:40:24 2019
| Host         : alfa-VirtualBox running 64-bit Ubuntu 16.04.2 LTS
| Command      : report_clocks
| Design       : fmk925926BenchmarkTop
| Device       : 7z020-clg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Clock Report


Attributes
  P: Propagated
  G: Generated
  V: Virtual
  I: Inverted

Clock       Period(ns)  Waveform(ns)    Attributes  Sources
clk_fpga_0  6.666       {0.000 3.333}   P           {PROCESSOR_INST/PROCESSING_SYSTEM_INST/system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}
clk_fpga_1  40.000      {0.000 20.000}  P           {PROCESSOR_INST/PROCESSING_SYSTEM_INST/system_i/processing_system7_0/inst/PS7_i/FCLKCLK[1]}
clk_fpga_2  5.333       {0.000 2.667}   P           {PROCESSOR_INST/PROCESSING_SYSTEM_INST/system_i/processing_system7_0/inst/PS7_i/FCLKCLK[2]}
clk_fpga_3  20.000      {0.000 10.000}  P           {PROCESSOR_INST/PROCESSING_SYSTEM_INST/system_i/processing_system7_0/inst/PS7_i/FCLKCLK[3]}


====================================================
Generated Clocks
====================================================



====================================================
User Uncertainty
====================================================



====================================================
User Jitter
====================================================

Clock       Jitter(ns)
clk_fpga_0  0.200
clk_fpga_1  1.200
clk_fpga_2  0.160
clk_fpga_3  0.600

Why is it so difficult? What's so wrong in renaming a variable?

 

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223 Views
Registered: ‎01-22-2015

Re: Rename PS7 clocks

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Marco,

       Why is it so difficult?
I feel your pain.  I was afraid that create_generated_clock would fail because UG903 says: “Only auto-derived clocks can be renamed with this mechanism” – and I couldn’t find that PS7 clocks are considered “auto-derived”.

I will continue to suggest to Xilinx that they somehow give us access to those read-only xdc-files, which would provide an easy solution to what you are trying to do.

Alas, I see no solution – sorry.

Mark

PS. I see the word “alfa” in your post.  I had a 1976 Alfa Romeo Spider Veloce for many years.  I really miss that car.

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Adventurer
Adventurer
197 Views
Registered: ‎10-02-2014

Re: Rename PS7 clocks

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Actually I don't see why a generic rename_object command cannot exist... as soon as the rename is processes all the subsequent constraints will need to use that new name...

to summarize the possible workarounds are:

1) Use a Tcl variable... but the friendly name will  not be used in the reports...

2) Override the constraint with a new  "create_clock"... but you will need to rewrite all the clock properties, frequency, jitter etc...

3)  Use the suggested Xilinx command that is "create_generated_clock"... but for some reason it works only with some kind of clock nets and not with others...

4) Take a deep breath ad live with it ... it's Xilinx software at the end, it's always been like this.

P.S.

We are not related to Alfa Romeo, but I live in nearby the former main factory (at the time of my Dad was one of the biggest of the northen Italy... now Alfa is FIAT and the factory is a mall), there is still a musem, if you stumble nearby Arese (Milano) you can visit it ;)

 

 

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188 Views
Registered: ‎01-22-2015

Re: Rename PS7 clocks

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Marco,

Thanks for nice summary of this thread and notes on Alfa Romeo!

In your first post to this thread, you showed the clocking constraints from the IP xdc-file, system_processing_system7_0_0.xdc. Try copying all these constraints into your project xdc-file. Then, in the copied version of the constraints, change the clock names (eg. from “-name clk_fpga_3” to “-name meaningful_name”).

The idea being that the project xdc-file will be processed by Vivado after the IP xdc-file. So, the version of the constraints in the project xdc-file should overwrite the constraints in the IP xdc-file.

Mark

 

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