04-21-2019 10:05 AM
I have requirement of connecting 24 PL to PS interrupts line in my design and I am using zynq ultrascale+. There are only total 16 bit interrupts present. I have concatenated two sets of 8 bits and connected it to the pl_ps_irq0 and pl_ps_irq1. So, can you tell me how to connect remaining 8 interrupts?
04-25-2019 12:25 AM
Hi @shanish ,
You need to route few PL peripheral interrupts through AXI concat IP to AXI interrupt controller to PS IRQ line.
This would help you to accomodate more that 16 interrupts.
04-25-2019 05:16 AM
We are already using the AXI Concat IP. But when we boot linux kernel it simple crashes on gic interrupt.
In our device tree we have not modified any property of AXI Interrupt. Do we need to declare the "interrupt-parent" property in device tree? we can define it but we donot know what to define in "interrupt" property because it should come automatically by HDF file but it is not coming.
Below is our design
04-26-2019 02:33 AM
Hi @shanish ,
Yes, in device tree you need to modify interrupt-parent. This doesnt automatically populated from DTG as two interrupt controllers are interfaced.
Please check all your interrupts are appropriately mapped with correct IDs or not in xparameter.h file before you make changes to device tree.
If you seeing build issue please refer to this https://www.xilinx.com/support/answers/68963.html .
04-26-2019 06:22 AM