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Contributor
Contributor
289 Views
Registered: ‎07-05-2017

Reqirement of extra PL to PS interrupt in Zynq Ultrascale+

Hi, 

I have requirement of connecting 24 PL to PS interrupts line in my design and I am using zynq ultrascale+. There are only total 16 bit interrupts present. I have concatenated two sets of 8 bits and connected it to the pl_ps_irq0 and pl_ps_irq1. So, can you tell me how to connect remaining 8 interrupts?

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Moderator
Moderator
221 Views
Registered: ‎07-31-2012

Re: Reqirement of extra PL to PS interrupt in Zynq Ultrascale+

Hi @shanish ,

You need to route few PL peripheral interrupts through AXI concat IP to AXI interrupt controller to PS IRQ line.

This would help you to accomodate more that 16 interrupts.

Regards

Praveen


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Contributor
Contributor
204 Views
Registered: ‎07-05-2017

Re: Reqirement of extra PL to PS interrupt in Zynq Ultrascale+

Hi Praveen,

We are already using the AXI Concat IP. But when we boot linux kernel it simple crashes on gic interrupt.

In our device tree we have not modified any property of AXI Interrupt. Do we need to declare the "interrupt-parent" property in device tree? we can define it but we donot know what to define in "interrupt" property because it should come automatically by HDF file but it is not coming.

Below is our design

design1.pngDesign

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Moderator
Moderator
169 Views
Registered: ‎07-31-2012

Re: Reqirement of extra PL to PS interrupt in Zynq Ultrascale+

Hi @shanish ,

Yes, in device tree you need to modify interrupt-parent. This doesnt automatically populated from DTG as two interrupt controllers are interfaced.

Please check all your interrupts are appropriately mapped with correct IDs or not in xparameter.h file before you make changes to device tree.

If you seeing build issue please refer to this https://www.xilinx.com/support/answers/68963.html .

Regards

Praveen


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Contributor
Contributor
158 Views
Registered: ‎07-05-2017

Re: Reqirement of extra PL to PS interrupt in Zynq Ultrascale+

Hi @pvenugo 

I have attached the xparameter.h of my design. Can you please tell me how do I infer the interrupt no. of axi_interrupt IP for writting in device tree.

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Moderator
Moderator
94 Views
Registered: ‎07-31-2012

Re: Reqirement of extra PL to PS interrupt in Zynq Ultrascale+

Hi @shanish ,

AXI INTC can take upto 32 interrupt signals as input. You may need to add rest of interrupt into concat IP > AXI INTC > PS GIC port.

Later need to verify the updated xparameter.h file. For e.g. your current xparameter.h file list interrupt and its ids correct.

13 interrupts - IDs 0 to 12.

You need to check in system.dtb/.dts file if the interrupt parent of this IRQs is intc. If not edit it and update.

Regards

Praveen

 


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