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SCL Frequency AXI IIC Bus Interface v2.0

Accepted Solution Solved
Observer
Posts: 23
Registered: ‎03-13-2018
Accepted Solution

SCL Frequency AXI IIC Bus Interface v2.0

Using Vivado v2018.1_AR70325 (64-bit), AXI IIC Bus Interface v2.0

ZYNQ-7 ZC706 Evaluation Board (xc7z045ffg900-2)

 

Configuring the IIC Parameters in the GUI for a “block design”, "AXI Clock Frequency (in MHz) (Auto) displays 100.0, it has a grey background and can't be changed. Is it “auto”, 100MHz or something else?

The actual AXI clock frequency is 125MHz.

The SCL Clock Frequency (in KHz) defaults to 100, that’s what I want.

When I try the I2C logic, according to the ILA, the SCL is 977,517 Hz, almost 10 times faster than it should be.

I tried decreasing the SCL clock frequency in the GUI so THIGH and TLOW could be increased. The SCL frequency could be reduced but it didn’t affect the width of the start, so that didn’t work.

A block design didn’t work, so I tried an RTL design. Configuring the IIC Parameters in the GUI for a RTL design, "AXI Clock Frequency (in MHz)” can be changed to 125.

When I try the I2C logic, according to the ILA, the SCL is 785,545.95 Hz instead of 100KHz.

An SCL of 785,545.95 Hz is not what I expected. It is not acceptable. Please advise.


Accepted Solutions
Moderator
Posts: 3,476
Registered: ‎11-09-2015

Re: SCL Frequency AXI IIC Bus Interface v2.0

Hi @mrpetep1,

 

In RLT, the configuration GUI should be different and should allow a change of the frequency. A generic or parameter should then be used under the hood

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.

View solution in original post


All Replies
Newbie
Posts: 2
Registered: ‎01-12-2018

Re: SCL Frequency AXI IIC Bus Interface v2.0

Hi, 

How did you fix it? I met the same problem. But the grey frequency is 25, I actually use 50MHz.

 

 

 

Newbie
Posts: 2
Registered: ‎01-12-2018

Re: SCL Frequency AXI IIC Bus Interface v2.0

Hi ,

 

Never mind. I found it will update automatically after you run synthesis. 

 

Cheers.

Observer
Posts: 23
Registered: ‎03-13-2018

Re: SCL Frequency AXI IIC Bus Interface v2.0

It didn't update for me, I couldn't figure out how to fix it. I gave up trying to use the IP.

Hope your project is a success!

 

Regards,

mrpetep1

Moderator
Posts: 3,476
Registered: ‎11-09-2015

Re: SCL Frequency AXI IIC Bus Interface v2.0

Hi @mrpetep1,

 

The AXI clock can be changed when you input a clock with a different frequency and update the Block Design.

 

The SCL should be expected to be set to the correct frequency if the AXI clock has the correct frequency.

 

How are you checking the frequency. Could you ouput the SCL clock and check outside the device?

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
Observer
Posts: 23
Registered: ‎03-13-2018

Re: SCL Frequency AXI IIC Bus Interface v2.0

Florent,

It didn't allow the AXI clock frequency to be changed even after saving, generating output products, running synthesis, etc.

 

I was checking the frequency with the ILA.

 

See first (‎06-07-2018 08:22 AM) post.

 

I assumed the marker position is displayed in ns. Is that correct?

 

Thank you,

mrpetep1

Highlighted
Moderator
Posts: 3,476
Registered: ‎11-09-2015

Re: SCL Frequency AXI IIC Bus Interface v2.0

[ Edited ]

HI @mrpetep1,

 

To change the AXI clock frequency you need to change the settings of your clock at the system level. If you clock is external to the BD you need to change the clock settings on the Block Design port settings and then validate the BD to propagate the setting to the AXI IIC (this is not set directly in the IP).

 

I assumed the marker position is displayed in ns. Is that correct?

No. In an ILA, the marker corresponds to 1 clock edge of your input clock. You do not have any notion of time unit in the ILA. So it will depends on your input clock. If the clock driving the ILA is 100MHz, then the scale will be 10 ns which might be what you expect

 

Hope that clarifies,

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
Observer
Posts: 23
Registered: ‎03-13-2018

Re: SCL Frequency AXI IIC Bus Interface v2.0

Florent,

The clock frequency is in (also) the BD port properties and the IP gets the frequency from there, it's displayed but not entered into the GUI. I understand, thanks.

 

I tried it in an RTL design, in that case would the frequency be in a generic integer or something? I don't recall.

 

In the ILA, the marker displays the number of clock domain clock cycles instead of time. I understand, thanks.

 

Regards,

mrpetep1

Moderator
Posts: 3,476
Registered: ‎11-09-2015

Re: SCL Frequency AXI IIC Bus Interface v2.0

Hi @mrpetep1,

 

In RLT, the configuration GUI should be different and should allow a change of the frequency. A generic or parameter should then be used under the hood

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.