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Visitor bijanbina
Visitor
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Registered: ‎03-05-2018

SDIO Length Matching - CLK

Hi, I'm designing a custom board around Zynq 7000 XC7Z020. In UG933 For the SDIO length matching it is recommended that

PCB and package delay skew for SD_DAT[0:3] and SD_CMD relative to SD_CLK must be between 50–200 ps.

 

I can't understand this line completely. Does it say that SD_DAT[0:3] and SD_CMD should be 50-200 ps longer than CLK signal? What is the best delay skew? because 50 to 200 ps is course for me. I can do length matching on my board better and with greater accuracy.

 

I checked out ZC702 reference design Allegro Brd file and from constraint manger extract following data.

2019-01-22 12_44_56-SDIO.xlsx - Excel.png

 It seems that all signal (CLK + Data + CMD) have matched to the same length and there is no sign of delay skew

 

 

 

 

 

 

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