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4,501 Views
Registered: ‎11-25-2016

SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

Hello. I'm working in a SPI testbed  with the following settings:

    XC72045 MASTER SPI  (SPI is on PS)
    XC72020 SLAVE SPI   (SPI is on PL build with VIVADO Intelletual Properties AXI_QUAD_SPI)

I'm trying to trasfer a file with a lenght of 512 bytes


Master and Slave are linked with a track of about 10cm

With this configuration i'm just able to receive 335 B on slave and 256 B on master. The remaining bytes are received dirty

On master SPI FIFO LENGHT TX-RX is 128
On slave SPI FIFO LENGHT TX-RX is 256

The only thing who pilots the transmission interrupt is fifo_queue_len=0 (no threshold)

I've used XILINX functions and default settings

Could you please help me to understand me what i'm doing wrong. My target is to be able, with this configuration, to transfer a file long about 15MB


Thanks in advance

 

Regards
Alessandro

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6 Replies
Teacher muzaffer
Teacher
4,485 Views
Registered: ‎03-31-2012

Re: SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

At 10 cm, it's possible that you are seeing signal integrity because of ringing at clock transitions. Do you have a series resistor on the spi clock signal? If not, try adding a 30-40 ohm series resistor between two fpga pins, preferably near the source. Another thing to check is the reference plane (ie ground) connections. What does your cabling look like? If you have enough wires, you can add more ground wires close to your spi wires.
Probably the best way to investigate the situation is to probe your spi signals with a scope, starting with the clock.
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Xilinx Employee
Xilinx Employee
4,454 Views
Registered: ‎07-23-2012

Re: SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

Please share the configurations of PS SPI andAXI Quad SPI. What instructions do you use to transmit the data?

Are you seeing any FULL/Empty flags set on either FIFOs?
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4,420 Views
Registered: ‎11-25-2016

Re: SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

We have tried different configurations varying fifo tx-rx depth , threshlod no-threshold, pre-scaler clock but we didn't obtaing good results.

I agree with you that seems to be a clock dis-alignment between master and slave but unfortunately i'm not able to use an oscilloscope because there's not enough space on the plane for the probes.

Could you provide me please a C source example code, including SPI initialization, for PS MASTER AND PL SLAVE so i can check it and use for my testbed.

I'm confident that your code has been tested for this kind of scenario.

Thanks in advance

 

Regards

Alessandro

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4,406 Views
Registered: ‎11-25-2016

Re: SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

This morning I've also tried to use xilinx functions example imported from SDK 2015.1.

 

For AXI_QUAD_SPI (with 2 differente tests) i've tried with

 

  1. xspi_slave_intr_slave
  2. xspi_slave_polled_example

 

For SPI_PS i've used

 

3. xspips_(flash)_intr_example substituting target flash with spi_slave (PL)

 

Unfortunately i've obtained the same results of my custom functions (perhaps obtained from xilinx example modifying parameters such as fifo depth , prescaler...).

I've used  xspi_slave_polled_example to verify that the problem wasn't on interrupt management.

How I could further investigate this problem.

Thanks

 

Alessandro

 

 

 

 

 

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4,369 Views
Registered: ‎11-25-2016

Re: SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

Regarding your question  about FIFO I've observed that FIFO TX of AXI QUAD SPI has:

 

  1. flag full set when, looking tx byte, there should be still space in the queue
  2. On polled scenario, once writes 128 byte and launched the sending procedure, empty-flag shows that queue never begins empty indicating a blocking transmission
  3. Data-abort event happens when we try to write a further byte on FIFO TX (that shouldn't be full)  during a writing cicle

 

Regards

Alessandro

 

 

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Adventurer
Adventurer
59 Views
Registered: ‎12-10-2014

Re: SPI: PS MASTER AND PL SLAVE TRANSFER JUST 128 BYTE

We're having the same issue with the Axi Quad SPI IP. Every now and then we get a data abort when writing to the SPI Data Transmit Register. It seems to happen only when the SDK debugger is being used. Any ideas of what is going on or how to debug?

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