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Explorer
Explorer
2,762 Views
Registered: ‎07-29-2009

SSIN tied high for EMIO SPI bus

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I see both this post:

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/about-this-warnning-When-using-EMIO-pins-for-SPI-0-tie-SSIN-High/m-p/688834#M12036

and the comment by ronnywebers at the bottom of this post:

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-ish-Chronicles-Part-81-Simple/ba-p/600617

 

Is the solution to "tying the EMIO pins for SPI_0 SSIN High in the PL bitstream" REALLY to use a constant in the block design?! I noticed no response to the first post.

 

Regards,

Kurt

 

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Explorer
Explorer
5,041 Views
Registered: ‎07-29-2009

Re: SSIN tied high for EMIO SPI bus

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That's a good idea.  I suppose connecting it to SS1 or SS2 would also be easier as well since I'm using SS0.

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Teacher muzaffer
Teacher
2,743 Views
Registered: ‎03-31-2012

Re: SSIN tied high for EMIO SPI bus

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@petersk if one is expanding the signals of an interface, the best solution to manage a tri-state connection which is used as output only is to connect the input to the signal to whatever is being driven at the output, ie connect SS_IN signal to SS_OUT and leave SS_TRI unconnected. This also makes the BD less cluttered as it's just a small short from out to in.

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Explorer
Explorer
5,042 Views
Registered: ‎07-29-2009

Re: SSIN tied high for EMIO SPI bus

Jump to solution

That's a good idea.  I suppose connecting it to SS1 or SS2 would also be easier as well since I'm using SS0.

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