06-19-2017 02:18 PM
In my other topic I was referred to AR #63381 about how Xilinx slave IPs require both the write address and data valid signals to go high at the same time before they're prepared to accept any requests. I'm taking that assertion on faith right now, though I will note that when I interfaced directly with the US+ MIG's AXI interface I was able to assert address valid and then data valid.
My question here is regarding the AXI smartconnect IP. In this instance, is the IP treated as if it is a slave device and requires both address and data valid to be asserted?
06-19-2017 02:26 PM
No. The AR is trying to say that many of the simple endpoint IP, like AXI GPIO, which were based on AXI Lite IPIF, may exhibit this behavior.
An the AR doesn't say they have to be asserted at the same time, but that the master is not allowed to have a dependency of one channel to another- that behavior is reserved for slave interfaces.