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Participant olkhramus
Participant
90 Views
Registered: ‎04-11-2019

Strange IIC IP AXI simulation behavior during write cycle to Transmit FIFO

I trying to simulate IIC IP in the Master mode in the Write Mode with the next testbench :

.........

// reset SR
tb.mpsoc_sys.Base_Zynq_MPSoC_i.zynq_ultra_ps_e_0.inst.read_data(32'hA0001104,4, read_data, resp);
//write CR , AXI IIC Enable = 1, MSMS = 1, Transmit Select = 1, TXAK = 0
tb.mpsoc_sys.Base_Zynq_MPSoC_i.zynq_ultra_ps_e_0.inst.write_data(32'hA0001100,4, 32'h0000000D, resp);
//write to TX FIFOtb.mpsoc_sys.Base_Zynq_MPSoC_i.zynq_ultra_ps_e_0.inst.write_data(32'hA0001108,4, 32'h0000015E, resp);

.........

TCL Consol report  everything was OK :

[5176] : M_AXI_HPM0_FPD : *ZYNQ_MPSoC_BFM_INFO : Starting Address(0xa0001104) -> AXI Read -> 4 bytes
[5416] : M_AXI_HPM0_FPD : *ZYNQ_MPSoC_BFM_INFO : Done AXI Read for Starting Address(0xa0001104) with Response 'OKAY'
[5416] : M_AXI_HPM0_FPD : *ZYNQ_MPSoC_BFM_INFO : Starting Address(0xa0001100) -> AXI Write -> 4 bytes
[5736] : M_AXI_HPM0_FPD : *ZYNQ_MPSoC_BFM_INFO : Done AXI Write for Starting Address(0xa0001100) with Response 'OKAY'
[5736] : M_AXI_HPM0_FPD : *ZYNQ_MPSoC_BFM_INFO : Starting Address(0xa0001108) -> AXI Write -> 4 bytes
[6046] : M_AXI_HPM0_FPD : *ZYNQ_MPSoC_BFM_INFO : Done AXI Write for Starting Address(0xa0001108) with Response 'OKAY'

but I don't see the expected value 0x 0000015E at S_AXI_WDATA during testbench last write cycle when I wrote data to transmit FIFO:

write_data(32'hA0001108,4, 32'h0000015E, ..) 

At the same time the write cycle to the CR ( address 0xA0001100)  is OK

 Is there the logical explanation?

 

 

 

 

 

Address_Map.png
testbench_fig.png
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1 Reply
Participant olkhramus
Participant
87 Views
Registered: ‎04-11-2019

Re: Strange IIC IP AXI simulation behavior during write cycle to Transmit FIFO

last line :

//write to TX FIFO

tb.mpsoc_sys.Base_Zynq_MPSoC_i.zynq_ultra_ps_e_0.inst.write_data(32'hA0001108,4, 32'h0000015E, resp);

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