10-23-2017 04:47 AM
Is it possible to mark some region of DDR memory (e.g. from 0x0FC00000 to 0x0FF00000) not to be cacheable neither by L1 nor by L2 ?
10-23-2017 07:18 PM
It is achieved with the setting of entries in the MMU translation table(s).
Could you provide more info on how you application is built?
I may be able to give you info on the changes to apply to set that region to non-cacheable (device or strongly ordered).
10-23-2017 10:56 PM
I supposed that... Unfortunately documentation about translation tables and Xil_SetTlbAttributes function is bit unclear...
Is there any examples for such functionality?
My app is writing to memory buffer in DDR and PL is reading this buffer. So I need to turn off caching of that region.
And I don't want to flush or disable DCache while writing to this buffer.
10-24-2017 10:19 AM
There is fair amount of info on Xil_SetTlbAttributes() in this doc:
You should also go through the "Virtual Memory System" section on the ARM v7 Architecture reference manual
As indicated in the first doc, table entries are 1M each, so to set 0x0FC00000 --> 0x0FF00000 you'll have to use Xil_SetTlbAttributes() 3 times (for 0x0FC00000, 0x0FD00000 and 0x0FE00000).
To disable the cache on L1 & L2, you'll have to use both INNER_NON_CACHE (L1) and OUTER_NON_CACHE (L2). and AP_FULL and SHAREABLE for full access
I think that should do it.