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Adventurer
Adventurer
7,251 Views
Registered: ‎01-13-2015

Testing Video in to AXI4 Stream IP

 

Hi all,

 

I'm testing 'Video in to AXI4 Stream' IP (V2S), but it does not work well.

 

I use TPG, VTC and AXI4 Stream to Video Out, and then this siganl directly connected to V2S.

And then another VTC and AXI4 Stream to Video Out are used to send that stream data to output device like Camera-Link.

 

This desing is to test Video in to AXI4 Stream' IP, other IPs work well. Only V2S does not work properly.

I changed FIFO depth, but this does not help.

 

The video size I use is 352x288(8bit mono) for video source. a clock is used to test video signals which is 20Mhz.

A board I use is ZC702.

 

I put a TCL file of this design, please, take a look and give me what is wrong with this design.

 

Thank you...

 

 

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3 Replies
Xilinx Employee
Xilinx Employee
7,235 Views
Registered: ‎08-01-2008

Re: Testing Video in to AXI4 Stream IP

For the configuration you described, you will want to want to use a single VTC to drive both of your AXI4-Stream to Video Out cores running in Master Mode. The AXI4-Stream to Video Out v3.0 Product Guide PG044 (Oct 2, 2013) has a good diagram, Figure 3-4, on page 22 on how to use the AXI4-Stream to Video out in Master Mode with a VDMA and Genlock. This would allow for your 2 outputs to be in sync using an external FSYNC signal. You should be able to generate this FSYNC input on the Generator side by using your VTC Detector when an FSYNC output turned on.
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
7,235 Views
Registered: ‎08-01-2008

Re: Testing Video in to AXI4 Stream IP

In situations where the AXI4 Lite interface is available for the AXI4-Stream to Video Out, the core can be reset or enabled through this software.

FID should be grounded for non-interlaced images.

If the core is not properly reset, there will not be output signals.

When the Video Data path includes VDMA:

AXI4-Stream to Video Out should be set to Master.

mm2s_HSIZE and mm2s_Stride in the VDMA should be set to bytes per line, not pixels per line.


When the Video Data path contains Video Scaler IP:

Ensure the input frame size of AXI4-Stream to Video Out is correct.

Ensure that the Clock frequency is fast enough to give Video Scaler enough time to process pixels.
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
7,214 Views
Registered: ‎01-13-2015

Re: Testing Video in to AXI4 Stream IP

Hi balkris,

 

Thank you for your response..

 

Right now, I dont' use VDMA, so there no issue of Sync siganl like Fsync.

 

I use two VTCs, because I need a video device like VGA or Camera that generates RGB, hsync vsync so on...

So TPG, Stream to video and the first VTC (in Master mode) wrapped up pretending a video device.

And then Video in to AXI4 Stream core receives video siganls from the "video device" and then passing to

AXI4-Stream to video core to display recived siganal.

 

This is to test AXI4-Stream to Video core on the testbench (simulation level). This is my plan.

 

Do you have any other comments with my issue?

 

Thank you

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