09-24-2015 04:53 PM
I'm testing 'Video in to AXI4 Stream' IP (V2S), but it does not work well.
I use TPG, VTC and AXI4 Stream to Video Out, and then this siganl directly connected to V2S.
And then another VTC and AXI4 Stream to Video Out are used to send that stream data to output device like Camera-Link.
This desing is to test Video in to AXI4 Stream' IP, other IPs work well. Only V2S does not work properly.
I changed FIFO depth, but this does not help.
The video size I use is 352x288(8bit mono) for video source. a clock is used to test video signals which is 20Mhz.
A board I use is ZC702.
I put a TCL file of this design, please, take a look and give me what is wrong with this design.
09-25-2015 12:20 AM
09-25-2015 12:21 AM
09-25-2015 01:48 PM
Thank you for your response..
Right now, I dont' use VDMA, so there no issue of Sync siganl like Fsync.
I use two VTCs, because I need a video device like VGA or Camera that generates RGB, hsync vsync so on...
So TPG, Stream to video and the first VTC (in Master mode) wrapped up pretending a video device.
And then Video in to AXI4 Stream core receives video siganls from the "video device" and then passing to
AXI4-Stream to video core to display recived siganal.
This is to test AXI4-Stream to Video core on the testbench (simulation level). This is my plan.
Do you have any other comments with my issue?