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Observer luckzzylb
Observer
1,665 Views
Registered: ‎08-14-2017

The connection of VCCO and I/O pins of an unused I/O bank in Zynq UltraScale+ MPSoCs

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Hello,

 

According to xtp427, all VCCO and I/O pins of an unused IO banks should be connected together to GND, a valid VCCO voltage, or a floating plane for maximum ESD protection.

VCCO of unused io bank_checklist.png

However, in AR# 11906, it says:

AR# 11906.png

So, does it mean the unused I/O pins and VCCO pins in the inner rows of the pin array can be left floating because the ESD events are unlikely and not considered a high risk?

 

For example, if bank65 and bank66 are unused, can we connect the outermost pins (the pins in the red frame) of these two banks to ground and leave the remaining pins (including VCCO pins ) of these two banks floating?

unused bank IO picture.png

 

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Community Manager
Community Manager
2,576 Views
Registered: ‎07-23-2015

Re: The connection of VCCO and I/O pins of an unused I/O bank in Zynq UltraScale+ MPSoCs

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@luckzzylb If you don't plan on using the Bank, have the VCCO pins connected to GND or floating plane in case you can't connect all IO pins to GND. I/O pins can be left floating. 

 

Each IO Pin has a upper clamp diode to VCCO and so by connecting VCCO to GND/floating plane, you are providing a path from the IO pin in case of an event. 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
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Community Manager
Community Manager
2,577 Views
Registered: ‎07-23-2015

Re: The connection of VCCO and I/O pins of an unused I/O bank in Zynq UltraScale+ MPSoCs

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@luckzzylb If you don't plan on using the Bank, have the VCCO pins connected to GND or floating plane in case you can't connect all IO pins to GND. I/O pins can be left floating. 

 

Each IO Pin has a upper clamp diode to VCCO and so by connecting VCCO to GND/floating plane, you are providing a path from the IO pin in case of an event. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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Voyager
Voyager
1,656 Views
Registered: ‎06-24-2013

Re: The connection of VCCO and I/O pins of an unused I/O bank in Zynq UltraScale+ MPSoCs

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Hey @luckzzylb,

 

So, does it mean the unused I/O pins and VCCO pins in the inner rows of the pin array can be left floating because the ESD events are unlikely and not considered a high risk?

That is how I'd interpret the "However ..." part, yes.

 

... can we connect the outermost pins to ground and leave the remaining pins floating?

I'd say that is what the "However ..." section implies.

 

But I wonder why you would want to do that in the first place instead of simply connecting them all together in a ground fill?

 

Best,

Herbert

-------------- Yes, I do this for fun!
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