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Contributor
Contributor
88 Views
Registered: ‎06-22-2018

Timing contraint for EMIO SPI and AXI SPI standard mode

As known the EMIO will route the signals between PL and PS, so do I need add timing contraints for EMIO SPI? And what about AXI SPI standar mode?

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Xilinx Employee
Xilinx Employee
56 Views
Registered: ‎07-12-2018

Re: Timing contraint for EMIO SPI and AXI SPI standard mode

Hi @diverger,

 

Please refer the below Answer Record for the timing constraints examples of SPI EMIO.

https://www.xilinx.com/support/answers/63174.html

Refer below link and go to page 89 

https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf

 

 

Best Regards
Abhinay PS
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